公开(公告)号：US20190259613A1

公开(公告)日：2019-08-22

申请号：US16402620

申请日：2019-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tsai-Chun Li ,  Huan-Just Lin ,  Huang-Ming Chen ,  Yang-Cheng Wu ,  Cheng-Hua Yang

IPC: H01L21/033 ,  H01L21/67 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/311 ,  G03F7/36 ,  G03F7/20 ,  H01J37/32 ,  H01L21/768

Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

公开(公告)号：US10312089B1

公开(公告)日：2019-06-04

申请号：US15923072

申请日：2018-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tsai-Chun Li ,  Huan-Just Lin ,  Huang-Ming Chen ,  Yang-Cheng Wu ,  Cheng-Hua Yang

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01J37/32 ,  G03F7/20 ,  G03F7/36 ,  H01L21/67

Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

公开(公告)号：US10692720B2

公开(公告)日：2020-06-23

申请号：US16679617

申请日：2019-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tsai-Chun Li ,  Huan-Just Lin ,  Huang-Ming Chen ,  Yang-Cheng Wu ,  Cheng-Hua Yang

IPC: H01L21/033 ,  G03F7/36 ,  G03F7/20 ,  H01J37/32 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L21/67

Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

公开(公告)号：US20200083046A1

公开(公告)日：2020-03-12

申请号：US16679617

申请日：2019-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tsai-Chun Li ,  Huan-Just Lin ,  Huang-Ming Chen ,  Yang-Cheng Wu ,  Cheng-Hua Yang

IPC: H01L21/033 ,  H01L21/67 ,  G03F7/36 ,  G03F7/20 ,  H01J37/32 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027

Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

公开(公告)号：US10050149B1

公开(公告)日：2018-08-14

申请号：US15598717

申请日：2017-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tsai-Chun Li ,  Ching-Feng Fu ,  Ming-Huan Tsai ,  D. T. Lee ,  Cheng-Hua Yang ,  Yi-Chen Lo

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/423

Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.