公开(公告)号：US20230207695A1

公开(公告)日：2023-06-29

申请号：US18175346

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/78391 ,  H01L21/02068 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7851 ,  H01L29/40111 ,  H01L29/66795

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20220077296A1

公开(公告)日：2022-03-10

申请号：US17532062

申请日：2021-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  Ziwei FANG ,  Chun-I WU ,  Huang-Lin CHAO

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

公开(公告)号：US20210328065A1

公开(公告)日：2021-10-21

申请号：US17362317

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20210193828A1

公开(公告)日：2021-06-24

申请号：US16718862

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06

Abstract: A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other.

公开(公告)号：US20210184008A1

公开(公告)日：2021-06-17

申请号：US17190236

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78

Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

公开(公告)号：US20210083120A1

公开(公告)日：2021-03-18

申请号：US16572255

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.

公开(公告)号：US20200373206A1

公开(公告)日：2020-11-26

申请号：US16739676

申请日：2020-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092 ,  H01L29/49 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/28

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.

公开(公告)号：US20200303549A1

公开(公告)日：2020-09-24

申请号：US16898659

申请日：2020-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Shahaji B. MORE ,  Cheng-Yi PENG ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ziwei FANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/06

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.

公开(公告)号：US20200294806A1

公开(公告)日：2020-09-17

申请号：US16353531

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor structure having metal contact features and a method for forming the same are provided. The method includes forming a dielectric layer covering an epitaxial structure over a semiconductor substrate and forming an opening in the dielectric layer to expose the epitaxial structure. The method includes forming a metal-containing layer over the dielectric layer and the epitaxial structure. The method includes heating the epitaxial structure and the metal-containing layer to transform a first portion of the metal-containing layer contacting the epitaxial structure into a metal-semiconductor compound layer. The method includes oxidizing the metal-containing layer to transform a second portion of the metal-containing layer over the metal-semiconductor compound layer into a metal oxide layer. The method includes applying a metal chloride-containing etching gas on the metal oxide layer to remove the metal oxide layer and forming a metal contact feature over the metal-semiconductor compound layer.

公开(公告)号：US20200083112A1

公开(公告)日：2020-03-12

申请号：US16687152

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei YU ,  Chia Ping LO ,  Liang-Gi YAO ,  Weng CHANG ,  Yee-Chia YEO ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/324 ,  H01L21/268 ,  H01L21/02 ,  H01L21/8234

Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.