公开(公告)号：US5524221A

公开(公告)日：1996-06-04

申请号：US311833

申请日：1994-09-23

申请人： Fumiki Sato ,  Kouichi Fujita

发明人： Fumiki Sato ,  Kouichi Fujita

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/226 ,  G06F9/321 ,  G06F9/3802

摘要： A microcomputer comprising an internal decoder for addressing instruction codes in an instruction prefetch buffer, a words field provided preferably in a micro ROM for storing number of words which indicate lengths of various instructions, and position calculating means provided in the bus interface unit for inputting the number of words to indicate an address of instruction code in the instruction prefetch buffer, so that the instruction code is read out concurrently with the execution of the micro instruction.

摘要翻译： 一种微型计算机，包括用于寻址指令预取缓冲器中的指令代码的内部解码器，优选地在微ROM中提供的字段，用于存储指示各种指令的长度的字数;以及位置计算装置，设置在总线接口单元中，用于输入 指示指令预取缓冲器中的指令代码的地址的字数，使得指令代码与微指令的执行同时读出。

公开(公告)号：US5483477A

公开(公告)日：1996-01-09

申请号：US205457

申请日：1994-03-04

申请人： Fumiki Sato ,  Kouichi Fujita

发明人： Fumiki Sato ,  Kouichi Fujita

IPC分类号： G06F7/49 ,  G06F7/48 ,  G06F7/52 ,  G06F7/533 ,  G06F7/00 ,  G06F15/00

CPC分类号： G06F7/5338 ,  G06F7/4824

摘要： A multiplying circuit wherein an adder 7 outputs a value "0" in which both of a positive part and a negative part of a number with a redundant code are "1", and at a last cycle of the multiplication cycles, the finish detecting circuit 13 detects finishing of multiplication cycles by detecting that "1" exists in a portion storing a positive part of a number with a redundant code of the third bit from the lowest bit of the second latch 8 and in a portion storing a negative part of the same at the same time. In such a construction, a counter circuit for counting multiplication cycles according to the Booth algorithm utilizing a number with a redundant code can be omitted. Accordingly, the number of transistors is reduced and the circuit configuration becomes simple.

摘要翻译： 乘法电路，其中加法器7输出其中具有冗余代码的数字的正部分和负部分都为“1”的值“0”，并且在乘法周期的最后一个周期，完成检测电路 13检测乘法周期的完成，通过检测在存储来自第二锁存器8的最低位的第三位的冗余代码的数字的正部分中存储的部分中存在“1”，并且存储负 同一时间。 在这种结构中，可以省略利用具有冗余码的数量的根据布斯算法进行乘法周期计数的计数器电路。 因此，晶体管的数量减少，电路结构变得简单。

公开(公告)号：US5038885A

公开(公告)日：1991-08-13

申请号：US350615

申请日：1989-05-11

申请人： Fumiki Sato ,  Hirofumi Iritani

发明人： Fumiki Sato ,  Hirofumi Iritani

IPC分类号： B60K17/348

CPC分类号： B60K17/348 ,  Y10T74/19279

摘要： In a four-wheel drive work vehicle selectively drivable in a standard four-wheel drive mode, an accelerated four-wheel drive mode and in a two-wheel drive mode, the invention provides an improved drive-mode switching operability through a linearly operable link mechanism for operatively connecting one operational system for directly operating a shift fork member with another operational system for operating the same via a cam member connected to a steering wheel.

摘要翻译： 在以标准四轮驱动模式选择性驱动的四轮驱动作业车辆中，加速四轮驱动模式和二轮驱动模式，本发明通过线性可操作的连杆提供改进的驱动模式切换操作性 用于可操作地连接一个操作系统的机构，用于将换档拨叉构件与用于通过连接到方向盘的凸轮构件的另一个操作系统直接操作。

公开(公告)号：US20050183501A1

公开(公告)日：2005-08-25

申请号：US10978785

申请日：2004-10-15

申请人： Kazutaka Saito ,  Akira Nakamuta ,  Ichiro Ueno ,  Fumiki Sato ,  Satoshi Hiyama

发明人： Kazutaka Saito ,  Akira Nakamuta ,  Ichiro Ueno ,  Fumiki Sato ,  Satoshi Hiyama

IPC分类号： G01C21/16 ,  G01P15/00 ,  G01P21/00 ,  G01P21/02

CPC分类号： G01P21/00 ,  G01C21/16

摘要： An inertia sensor unit having a detecting element, a signal processor being constituted as an element separate from the detecting element, for at least amplifying signals output from the detecting element, and an inertia sensor mounted to a detection object for detecting acceleration or angular velocity of the detection object as an inertial force of the detection object to output electrical signals changing according to the inertial force, includes: a first temperature detecting means for detecting the temperature of the signal processor, a second temperature detecting means for detecting the temperature of the detecting element directly or indirectly, and a correcting means for correcting the signals output from the inertia sensor based on the result detected by the first temperature detecting means and the second temperature detecting means.

摘要翻译： 惯性传感器单元，具有检测元件，信号处理器构成为与检测元件分离的元件，用于至少放大从检测元件输出的信号;以及惯性传感器，安装在检测对象上，用于检测加速度或角速度 作为检测对象的惯性力的检测对象输出根据惯性力而变化的电信号，包括：检测信号处理器的温度的第一温度检测单元，检测检测对象的温度的第二温度检测单元 以及校正装置，用于基于由第一温度检测装置和第二温度检测装置检测到的结果来校正从惯性传感器输出的信号。

公开(公告)号：US5926037A

公开(公告)日：1999-07-20

申请号：US890619

申请日：1997-07-09

申请人： Fumiki Sato ,  Kouichi Fujita

发明人： Fumiki Sato ,  Kouichi Fujita

IPC分类号： G11C11/417 ,  G11C19/00 ,  H03K3/037 ,  H03K3/356 ,  H03K19/0175 ,  G11C7/00 ,  H03K19/094

CPC分类号： H03K3/356191

摘要： A buffer circuit which can solve a problem of a conventional buffer circuit in that high speed data transfer is hindered because of parasitic capacitance of signal lines, which has an affect on the discharge time of inverters in a latch circuit of the buffer circuit, when the buffer circuit changes its state from a first term (non-transfer mode) to a second term (transfer mode). The buffer circuit solves this problem by pouring a current, which flows thereinto from a first signal line, into ground through a first PMOS transistor, a first NMOS transistor and a third NMOS transistor, and by pouring a current, which flows thereinto from a second signal line, into the ground through a second PMOS transistor, a second NMOS transistor and the third NMOS transistor.

摘要翻译： 由于在对缓冲电路的锁存电路中的反相器的放电时间产生影响的信号线的寄生电容的情况下，可以解决在该高速数据传输中解决现有的缓冲电路的问题的缓冲电路， 缓冲电路将其状态从第一项（非转移模式）改变为第二项（传输模式）。 缓冲电路通过将从第一信号线流入的电流通过第一PMOS晶体管，第一NMOS晶体管和第三NMOS晶体管注入接地来解决这个问题，并且通过从第二PMOS晶体管，第一NMOS晶体管和第三NMOS晶体管中流入的电流 信号线通过第二PMOS晶体管，第二NMOS晶体管和第三NMOS晶体管插入地。

公开(公告)号：US5721504A

公开(公告)日：1998-02-24

申请号：US538944

申请日：1995-10-04

申请人： Fumiki Sato

发明人： Fumiki Sato

IPC分类号： H03F3/345 ,  H03K5/007 ,  H03K5/08

CPC分类号： H03K5/08 ,  H03K5/007

摘要： The invention provides a clamping semiconductor circuit in which a first transistor of one conductivity type and a second transistor of another conductivity type are connected in series to each other and interposed between a power supply terminal and a signal line. The second transistor is supplied with a predetermined voltage, thereby allowing a current to flow from a power supply to the signal line. When the voltage of the signal line becomes equal to the predetermined voltage, all the transistors become nonconductive, thereby cutting off an unwanted current flowing from a power supply into the signal line.

摘要翻译： 本发明提供了一种钳位半导体电路，其中一种导电类型的第一晶体管和另一种导电类型的第二晶体管彼此串联连接并插入在电源端子和信号线之间。 第二晶体管被提供预定电压，从而允许电流从电源流向信号线。 当信号线的电压变得等于预定电压时，所有的晶体管都变成非导通的，从而切断从电源流入信号线的有害电流。

公开(公告)号：US5479632A

公开(公告)日：1995-12-26

申请号：US248833

申请日：1994-05-25

申请人： Fumiki Sato ,  Kouichi Fujita

发明人： Fumiki Sato ,  Kouichi Fujita

IPC分类号： G06F9/35 ,  G06F9/22 ,  G06F9/30 ,  G06F12/02 ,  G06F15/78 ,  G06F12/08

CPC分类号： G06F9/223 ,  G06F9/30149

摘要： A microcomputer includes a layered memory having a higher layer for storing a series of instructions forming a program to be executed by the microcomputer and a lower layer, having an upside layer accessed by ID information in the instructions stored in the higher layer memory, and a downside layer, accessed by the upside layer, having a sequence of storage locations storing code data for controlling the execution unit to calculate effective addresses.

摘要翻译： 微型计算机包括具有更高层的分层存储器，用于存储形成由微计算机执行的程序的一系列指令和具有通过存储在较高层存储器中的指令中的ID信息访问的上层的下层，以及 下侧层，由上侧层访问，具有存储代码数据的一系列存储位置，用于控制执行单元计算有效地址。

公开(公告)号：US5442801A

公开(公告)日：1995-08-15

申请号：US147269

申请日：1993-11-05

申请人： Fumiki Sato ,  Kouichi Fujita

发明人： Fumiki Sato ,  Kouichi Fujita

IPC分类号： G06F7/505 ,  G06F7/575 ,  G06F7/38

CPC分类号： G06F7/575

摘要： An arithmetic and logic unit is provided with a first NAND gate (29) which outputs a NAND logic operation result between a first operand (A.sub.i), a second operand (B.sub.i) and a first control signal (S.sub.0), a first EXOR gate (30) which outputs an EXOR logic operation result between the output of the first NAND gate (29) and a second control signal (S.sub.1), an OR gate (31) which outputs an OR logic operation result between the first operand (A.sub.i) and the second operand (B.sub.i), a second NAND gate (32) which outputs a NAND logic operation result between the output of the first EXOR gate (30) and the output of the OR gate (31), a third NAND gate (20) which outputs a NAND logic operation result between a third control signal (S.sub.2) and a carry input (CY.sub.i-1), and a second EXOR gate (21) which outputs an EXOR logic operation result between the output of the second NAND gate (32) and the output of the third NAND gate (20), so that OR, EXOR and AND logic operations and ADD arithmetic operation for the both operands (A.sub.i and B.sub.i) are executed.

摘要翻译： 算术和逻辑单元设置有第一NAND门（29），其输出第一操作数（Ai），第二操作数（B 1）和第一控制信号（S 0）之间的与非逻辑运算结果，第一异或门（ 30），其输出第一与非门（29）的输出和第二控制信号（S1）之间的EXOR逻辑运算结果;或门（31），其输出第一操作数（Ai）与第 第二操作数（Bi），在第一EXOR门（30）的输出与或门（31）的输出之间输出NAND逻辑运算结果的第二NAND门（32），第三NAND门（20） 其输出第三控制信号（S2）和进位输入（CYi-1）之间的NAND逻辑运算结果;以及第二异或门（21），其在第二与非门（32）的输出之间输出EXOR逻辑运算结果 ）和第三与非门（20）的输出，使得OR，EXOR和AND逻辑运算和ADD算术运算为两个运算 （Ai和Bi）。

公开(公告)号：US5423012A

公开(公告)日：1995-06-06

申请号：US977947

申请日：1992-11-18

申请人： Fumiki Sato ,  Kouichi Fujita

发明人： Fumiki Sato ,  Kouichi Fujita

IPC分类号： G06F9/305 ,  G06F9/30 ,  G06F9/38 ,  G06F9/00 ,  G06F13/00

CPC分类号： G06F9/3814 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3802

摘要： In a microcomputer, for using all the instruction words having uniform word length, a first or second instruction word stored in a memory area of a memory indicated by an address of an address register is read in a predetermined word position of an instruction first-reading buffer indicated by a first pointer and the first or second instruction word read from a word position of the instruction first-reading buffer indicated by a second pointer is read in an instruction interpreting section through a second shifter. This instruction interpreting section interprets an instruction word from a bus interface section. In the case of the second instruction word (data instruction), data necessary for a calculation are produced on the basis of data of the second instruction word such as immediate data and offset data. In the case of the first instruction word, a calculation is effected on the basis of data produced by a data expansion section.

摘要翻译： 在微型计算机中，为了使用具有均匀字长的所有指令字，存储在由地址寄存器的地址指示的存储器的存储区域中的第一或第二指令字被读入指令第一读取的预定字位置 通过第二移位器在指令解释部分中读取由第一指针指示的缓冲器和从第二指针指示的指令第一读取缓冲器的字位置读取的第一或第二指令字。 该指令解释部分解释来自总线接口部分的指令字。 在第二指令字（数据指令）的情况下，基于诸如立即数据和偏移数据的第二指令字的数据产生计算所需的数据。 在第一指令字的情况下，基于由数据扩展部产生的数据进行计算。

公开(公告)号：USD440235S1

公开(公告)日：2001-04-10

申请号：US29110776

申请日：1999-09-13

申请人： Junta Kuwae ,  Fumiki Sato ,  Toshihiko Takemura ,  Yasuo Nakata ,  Takeshi Kajimoto

设计人： Junta Kuwae ,  Fumiki Sato ,  Toshihiko Takemura ,  Yasuo Nakata ,  Takeshi Kajimoto