公开(公告)号：US10720490B2

公开(公告)日：2020-07-21

申请号：US16732371

申请日：2020-01-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin ,  Jiao Jia ,  Yunlong Liu ,  Manoj Jain

IPC: H01L49/02 ,  H01L21/02 ,  H01L23/495 ,  H01L29/94

Abstract: A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

公开(公告)号：US10692822B2

公开(公告)日：2020-06-23

申请号：US16372117

申请日：2019-04-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin

IPC: H01L29/861 ,  H01L29/15 ,  H01L27/02 ,  H01L29/868 ,  H01L23/60

Abstract: In some examples, an electrostatic discharge (ESD) device includes a substrate layer, a transition layer positioned on the substrate layer, a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers. The ESD device further includes a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, where a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, where the plurality of doped contact structures are to generate a zero capacitance ESD device.

公开(公告)号：US09865584B1

公开(公告)日：2018-01-09

申请号：US15344087

申请日：2016-11-04

Applicant: Texas Instruments Incorporated

Inventor： He Lin ,  Kun Chen ,  Chao Wu ,  Dening Wang ,  Lily Springer ,  Andy Strachan ,  Gang Xue

IPC: H01L27/02 ,  H01L27/08 ,  H01L29/866 ,  H01L29/06

CPC classification number: H01L27/0248 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/866

Abstract: A contact array optimization scheme for ESD devices. In one embodiment, contact apertures patterned through a pre-metal dielectric layer over active areas may be selectively modified in size, shape, placement and the like, to increase ESD protection performance, e.g., such as maximizing the transient current density, etc., in a standard ESD rating test.