公开(公告)号：US20190229074A1

公开(公告)日：2019-07-25

申请号：US16372117

申请日：2019-04-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin

IPC: H01L23/60 ,  H01L29/868 ,  H01L27/02 ,  H01L29/15

CPC classification number: H01L23/60 ,  H01L27/0255 ,  H01L29/15 ,  H01L29/157 ,  H01L29/861 ,  H01L29/868

Abstract: In some examples, an electrostatic discharge (ESD) device includes a substrate layer, a transition layer positioned on the substrate layer, a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers. The ESD device further includes a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, where a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, where the plurality of doped contact structures are to generate a zero capacitance ESD device.

公开(公告)号：US20210408306A1

公开(公告)日：2021-12-30

申请号：US17474492

申请日：2021-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin ,  Sameer Pendharkar

IPC: H01L31/0352 ,  H01L31/0224 ,  H01L31/0216 ,  H01L31/02 ,  H01L27/144 ,  H01L31/103 ,  H01L31/0304 ,  H01L25/04 ,  H01L31/18

Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.

公开(公告)号：US10586844B2

公开(公告)日：2020-03-10

申请号：US16021123

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： He Lin ,  Jiao Jia ,  Yunlong Liu ,  Manoj Jain

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/495

Abstract: A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

公开(公告)号：US10559650B2

公开(公告)日：2020-02-11

申请号：US16028862

申请日：2018-07-06

Applicant: Texas Instruments Incorporated

Inventor： Jiao Jia ,  Zhipeng Feng ,  He Lin ,  Yunlong Liu ,  Manoj Jain

IPC: H01L49/02 ,  H01L21/306 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/3213 ,  H01L23/495 ,  H01L23/00 ,  H01L21/3205 ,  H01L25/18 ,  H01L29/78

Abstract: A trench capacitor includes a plurality of trenches in a doped semiconductor surface layer of a substrate. At least one dielectric layer lines a surface of the plurality of trenches. A second polysilicon layer that is doped is on a first polysilicon layer that is on the dielectric layer which fills the plurality of trenches. The second polysilicon layer has a higher doping level as compared to the first polysilicon layer.

公开(公告)号：US20240142512A1

公开(公告)日：2024-05-02

申请号：US17978170

申请日：2022-10-31

Applicant: Texas Instruments Incorporated

Inventor： Zhi Peng Feng ,  Ren Hui Fan ,  Alfred Griffin ,  He Lin

IPC: G01R31/265 ,  G01R31/26

CPC classification number: G01R31/2656 ,  G01R31/2601

Abstract: A semiconductor device testing system, with a platform for supporting a semiconductor substrate, a light emitting system directed toward the platform, a controller, coupled to the light emitting system and adapted to selectively alter an operational parameter of the light emitting system, and a tester configured to characterize an electrical parameter of an electrical device formed in or over the semiconductor substrate while the electrical device is illuminated by one or more wavelengths of light emitted by the light emitting system under direction of the controller.

公开(公告)号：US20210005763A1

公开(公告)日：2021-01-07

申请号：US16502108

申请日：2019-07-03

Applicant: Texas Instruments Incorporated

Inventor： He Lin ,  Sameer Pendharkar

IPC: H01L31/0352 ,  H01L31/0224 ,  H01L31/0216 ,  H01L31/02 ,  H01L27/144 ,  H01L31/18 ,  H01L31/0304 ,  H01L25/04 ,  H01L31/103

Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.

公开(公告)号：US11978814B2

公开(公告)日：2024-05-07

申请号：US17474492

申请日：2021-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin ,  Sameer Pendharkar

IPC: H01L31/0352 ,  H01L25/04 ,  H01L27/144 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/103 ,  H01L31/18

CPC classification number: H01L31/035236 ,  H01L25/042 ,  H01L27/1443 ,  H01L27/1446 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/02164 ,  H01L31/022408 ,  H01L31/03048 ,  H01L31/1035 ,  H01L31/1848 ,  H01L31/1852

Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.

公开(公告)号：US11271072B2

公开(公告)日：2022-03-08

申请号：US16774014

申请日：2020-01-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jiao Jia ,  Zhipeng Feng ,  He Lin ,  Yunlong Liu ,  Manoj Jain

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/3213 ,  H01L23/495 ,  H01L23/00 ,  H01L21/3205 ,  H01L25/18 ,  H01L21/306 ,  H01L29/78 ,  H01L23/31

Abstract: A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.

公开(公告)号：US10312202B2

公开(公告)日：2019-06-04

申请号：US15805897

申请日：2017-11-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin

IPC: H01L23/60 ,  H01L29/868 ,  H01L27/02 ,  H01L29/15

Abstract: In some examples, an electrostatic discharge (ESD) device includes a substrate layer, a transition layer positioned on the substrate layer, a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers. The ESD device further includes a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, where a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, where the plurality of doped contact structures are to generate a zero capacitance ESD device.

公开(公告)号：US11158750B2

公开(公告)日：2021-10-26

申请号：US16502108

申请日：2019-07-03

Applicant: Texas Instruments Incorporated

Inventor： He Lin ,  Sameer Pendharkar

IPC: H01L31/0352 ,  H01L31/0224 ,  H01L31/0216 ,  H01L31/02 ,  H01L27/144 ,  H01L31/103 ,  H01L31/0304 ,  H01L25/04 ,  H01L31/18

Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.