公开(公告)号：US10720490B2

公开(公告)日：2020-07-21

申请号：US16732371

申请日：2020-01-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin ,  Jiao Jia ,  Yunlong Liu ,  Manoj Jain

IPC: H01L49/02 ,  H01L21/02 ,  H01L23/495 ,  H01L29/94

Abstract: A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

公开(公告)号：US10586844B2

公开(公告)日：2020-03-10

申请号：US16021123

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： He Lin ,  Jiao Jia ,  Yunlong Liu ,  Manoj Jain

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/495

Abstract: A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

公开(公告)号：US10559650B2

公开(公告)日：2020-02-11

申请号：US16028862

申请日：2018-07-06

Applicant: Texas Instruments Incorporated

Inventor： Jiao Jia ,  Zhipeng Feng ,  He Lin ,  Yunlong Liu ,  Manoj Jain

IPC: H01L49/02 ,  H01L21/306 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/3213 ,  H01L23/495 ,  H01L23/00 ,  H01L21/3205 ,  H01L25/18 ,  H01L29/78

Abstract: A trench capacitor includes a plurality of trenches in a doped semiconductor surface layer of a substrate. At least one dielectric layer lines a surface of the plurality of trenches. A second polysilicon layer that is doped is on a first polysilicon layer that is on the dielectric layer which fills the plurality of trenches. The second polysilicon layer has a higher doping level as compared to the first polysilicon layer.

公开(公告)号：US09607926B2

公开(公告)日：2017-03-28

申请号：US14563085

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Manoj Jain

IPC: H01L21/66 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a probe pad with a plurality of pad segments. The pad segments are elements of an interconnect level of the wafer.

公开(公告)号：US11271072B2

公开(公告)日：2022-03-08

申请号：US16774014

申请日：2020-01-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jiao Jia ,  Zhipeng Feng ,  He Lin ,  Yunlong Liu ,  Manoj Jain

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/3213 ,  H01L23/495 ,  H01L23/00 ,  H01L21/3205 ,  H01L25/18 ,  H01L21/306 ,  H01L29/78 ,  H01L23/31

Abstract: A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.