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11.发明申请SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER 有权用于提供可编程QUIESCE FILTERING寄存器的系统，方法和计算机程序产品公开(公告)号：US20120144154A1
公开(公告)日：2012-06-07
申请号：US13372603
申请日：2012-02-14
IPC分类号： G06F12/10
CPC分类号： G06F9/4812
摘要： Storing translation lookaside buffer (TLB) entries are in a TLB1 at the processor. The TLB1 includes entries associated with main storage accesses of programs executing in a guest mode in a current zone and entries associated with main storage accesses of firmware executing in a host mode. A quiesce interruption request is received at the processor that includes a requesting zone indicator. The processor is either executing in the host mode and has no zone or in the guest mode with the current zone. The requesting zone indicator and the contents of a programmable filtering register that indicates exceptions to filtering performed by the processor is used to determine if filtering should be performed. The quiesce interruption request may be filtered based on the requesting zone indicator even after the mode switches from the guest mode to the host mode.
摘要翻译： 存储翻译后备缓冲区（TLB）条目位于处理器的TLB1中。 TLB1包括与在当前区域中以访客模式执行的程序的主存储访问相关联的条目和与以主机模式执行的固件的主存储访问相关联的条目。 在包括请求区域指示符的处理器处接收到静默中断请求。 处理器正在主机模式下执行，并且没有区域，或者在访问模式下使用当前区域。 请求区域指示符和指示处理器执行的过滤异常的可编程过滤寄存器的内容用于确定是否应执行过滤。 即使模式从客户模式切换到主机模式，也可以基于请求区域指示符来过滤停顿中断请求。
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12.发明授权System, method and computer program product for providing a programmable quiesce filtering register 有权用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品公开(公告)号：US08332614B2
公开(公告)日：2012-12-11
申请号：US13372603
申请日：2012-02-14
IPC分类号： G06F12/10
CPC分类号： G06F9/4812
摘要： Storing translation lookaside buffer (TLB) entries are in a TLB1 at the processor. The TLB1 includes entries associated with main storage accesses of programs executing in a guest mode in a current zone and entries associated with main storage accesses of firmware executing in a host mode. A quiesce interruption request is received at the processor that includes a requesting zone indicator. The processor is either executing in the host mode and has no zone or in the guest mode with the current zone. The requesting zone indicator and the contents of a programmable filtering register that indicates exceptions to filtering performed by the processor is used to determine if filtering should be performed. The quiesce interruption request may be filtered based on the requesting zone indicator even after the mode switches from the guest mode to the host mode.
摘要翻译： 存储翻译后备缓冲区（TLB）条目位于处理器的TLB1中。 TLB1包括与在当前区域中以访客模式执行的程序的主存储访问相关联的条目和与以主机模式执行的固件的主存储访问相关联的条目。 在包括请求区域指示符的处理器处接收到静默中断请求。 处理器正在主机模式下执行，并且没有区域，或者在访问模式下使用当前区域。 请求区域指示符和指示处理器执行的过滤异常的可编程过滤寄存器的内容用于确定是否应执行过滤。 即使模式从客户模式切换到主机模式，也可以基于请求区域指示符来过滤停顿中断请求。
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13.发明授权System, method and computer program product for providing a programmable quiesce filtering register 失效用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品公开(公告)号：US08140834B2
公开(公告)日：2012-03-20
申请号：US12037808
申请日：2008-02-26
CPC分类号： G06F9/4812
摘要： A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.
摘要翻译： 一种用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品。 该方法包括在处理器处接收静止中断请求。 处理器正在以一种模式执行。 识别与该模式相关联的过滤区域。 确定处理器是否可以过滤停顿中断请求。 该确定响应于过滤区域和可编程过滤寄存器的内容，用于指示接收处理器执行的过滤异常。 响应于确定可以对请求进行过滤，过滤掉静默中断请求。
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14.发明申请SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER 失效用于提供可编程QUIESCE FILTERING寄存器的系统，方法和计算机程序产品公开(公告)号：US20090216929A1
公开(公告)日：2009-08-27
申请号：US12037808
申请日：2008-02-26
IPC分类号： G06F13/24
CPC分类号： G06F9/4812
摘要： A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.
摘要翻译： 一种用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品。 该方法包括在处理器处接收静止中断请求。 处理器正在以一种模式执行。 识别与该模式相关联的过滤区域。 确定处理器是否可以过滤停顿中断请求。 该确定响应于过滤区域和可编程过滤寄存器的内容，用于指示接收处理器执行的过滤异常。 响应于确定可以对请求进行过滤，过滤掉静默中断请求。
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15.发明授权Method, system and program product for clearing selected storage translation buffer entries 有权清除所选存储转换缓冲区条目的方法，系统和程序产品公开(公告)号：US07281115B2
公开(公告)日：2007-10-09
申请号：US11204321
申请日：2005-08-15
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/3824 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/683
摘要： An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
摘要翻译： 提供指令来执行与特定地址空间相关联的所选地址转换缓冲器条目（TLB条目）的清除，诸如存储段或存储区域。 缓冲区条目与段表项或区域表项或ASCE地址相关。 该指令可以通过软件仿真，硬件，固件或其组合来实现。
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16.发明授权Perform frame management function instruction for setting storage keys and clearing blocks of main storage 有权执行用于设置存储键和清除主存储块的帧管理功能指令公开(公告)号：US08417916B2
公开(公告)日：2013-04-09
申请号：US11972725
申请日：2008-01-11
申请人： Dan F. Greiner , Charles W. Gainey, Jr. , Lisa C. Heller , Damian L. Osisek , Timothy J. Slegel , Gustav E. Sittmann
发明人： Dan F. Greiner , Charles W. Gainey, Jr. , Lisa C. Heller , Damian L. Osisek , Timothy J. Slegel , Gustav E. Sittmann
IPC分类号： G06F12/08
CPC分类号： G06F12/1475 , G06F9/3004 , G06F9/30047 , G06F9/30145 , G06F12/10
摘要： What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.
摘要翻译： 公开的是针对计算机系统的机器结构定义的集合关键和清晰的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的机器指令。 从第一通用寄存器获得的是指示存储帧是小块还是大块数据的帧大小字段。 从第二通用寄存器获得的是要执行指令的存储帧的操作数地址。 如果存储帧是小块，则仅在小块上执行指令。 如果指示的存储帧是大数据块，则从第二通用寄存器获得大数据块内的初始第一数据块的操作数地址。 在从初始第一块开始的所有块上执行帧管理指令。
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公开(公告)号：US20120166758A1
公开(公告)日：2012-06-28
申请号：US13412889
申请日：2012-03-06
申请人： Dan F. Greiner , Charles W Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Timothy J. Slegel , Gustav E. Sittmann
发明人： Dan F. Greiner , Charles W Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Timothy J. Slegel , Gustav E. Sittmann
IPC分类号： G06F12/10
CPC分类号： G06F12/1475 , G06F9/30003 , G06F9/3004 , G06F9/30145 , G06F12/00 , G06F12/023 , G06F12/10 , G06F12/1027 , G06F12/145 , G06F2212/68
摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.
摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的帧管理指令。 第一通用寄存器包含具有带有访问保护位的密钥字段和块大小指示的帧管理字段。 如果块大小指示指示大块，则从第二通用寄存器获得大数据块的操作数地址。 大块数据具有多个小块，每个小块与具有多个存储密钥访问保护位的对应存储密钥相关联。 如果块大小指示指示大块，则使用密钥字段的访问保护位来设置大块内的每个小块的每个相应的存储密钥的存储密钥访问保护位。
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18.发明申请公开(公告)号：US20120137106A1
公开(公告)日：2012-05-31
申请号：US13336106
申请日：2011-12-23
申请人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.
摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的索引部分用于引用转换表中的条目。 如果启用了转换表条目中包含的格式控制字段，则表项包含大小至少为1M字节的大块数据的帧地址。 然后将帧地址与虚拟地址的偏移部分组合以形成主存储器或存储器中的小4K字节数据块的转换地址。
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19.发明申请FUNCTION VIRTUALIZATION FACILITY FOR BLOCKING INSTRUCTION FUNCTION OF A MULTI-FUNCTION INSTRUCTION OF A VIRTUAL PROCESSOR 审中-公开用于阻止虚拟处理器的多功能指令的指令功能的功能虚拟化设施公开(公告)号：US20110320773A1
公开(公告)日：2011-12-29
申请号：US12822368
申请日：2010-06-24
IPC分类号： G06F9/30
摘要： In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.
摘要翻译： 在支持执行指令的多个功能的处理器中，设置用于阻止多个功能中的一个或多个的指令阻塞值，使得执行阻塞功能之一的尝试将导致程序异常，并且 该指令将不会执行，但是相同的指令将能够执行任何未被阻止的功能的功能。
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20.发明授权Load page table entry address instruction execution based on an address translation format control field 有权基于地址转换格式控制字段加载页表项目地址指令执行公开(公告)号：US08041923B2
公开(公告)日：2011-10-18
申请号：US11972700
申请日：2008-01-11
申请人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Gustav E. Sittmann
发明人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Gustav E. Sittmann
CPC分类号： G06F12/1027 , G06F12/1009 , G06F2212/651 , G06F2212/652
摘要： What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.
摘要翻译： 提供了为计算机系统的机器结构定义的加载页表项地址函数。 在一个实施例中，获得机器指令，其中包含指示要执行加载页表项地址函数的操作码。 机器指令包含M字段，标识第一通用寄存器的第一字段和标识第二通用寄存器的第二字段。 基于M场的内容，获得具有至少一个段表的地址转换表的层次结构的初始起始地址。 基于获得的初始起始地址，执行动态地址转换，直到获得页表项。 页表入口地址保存在识别的第一个通用寄存器中。
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