DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
    11.
    发明申请
    DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
    数字适配​​电路和可编程逻辑器件的方法

    公开(公告)号:US20110188564A1

    公开(公告)日:2011-08-04

    申请号:US13079420

    申请日:2011-04-04

    IPC分类号: H03K5/125 H03K5/19

    CPC分类号: H04L25/03885

    摘要: Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

    摘要翻译: 输入数据信号的均衡可以通过在该信号中的数据值应当稳定(“数据采样”)的时候对该信号进行采样来控制,并且当该信号应该在不同的连续数据值(“转换样本” )。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值(可以是这两个数据样本之一)进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

    Signal offset cancellation
    12.
    发明授权
    Signal offset cancellation 有权
    信号偏移消除

    公开(公告)号:US07898313B1

    公开(公告)日:2011-03-01

    申请号:US12723450

    申请日:2010-03-12

    IPC分类号: H03F3/45 H03L5/00

    摘要: Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.

    摘要翻译: 提供技术和电路用于可编程地控制集成电路中的信号偏移。 在一个实施例中,集成电路包括可编程地选择以控制放大器电路的一个输入/输出或另一个输入/输出上的信号的偏移的信号偏移消除电路。 在一个实施例中,逻辑电路用于通过开关电路将一组电流源选择性地耦合到差分放大器的一个输入/输出或另一个输入/输出。 可以采用电流源的组来控制输入/输出上的信号偏移,或者当不需要信号偏移消除时可以与所有的输入/输出去耦。

    Half-rate DFE with duplicate path for high data-rate operation
    13.
    发明授权
    Half-rate DFE with duplicate path for high data-rate operation 有权
    具有高数据速率操作的重复路径的半速率DFE

    公开(公告)号:US07782935B1

    公开(公告)日:2010-08-24

    申请号:US11514490

    申请日:2006-08-31

    IPC分类号: H03H7/30

    摘要: Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.

    摘要翻译: 提出了用于向高数据速率信号提供均衡的方法和电路,包括判决反馈均衡(DFE)。 半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。 可以使用以输入信号数据速率的一半工作的两个延迟链电路。 更一般地,可以使用以1 / n输入信号数据速率工作的n个延迟链电路。 多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。 重复路径DFE电路包括用于提供DFE均衡的两个路径,同时减少DFE电路之前的电路上的DFE电路的负载。 第一路径产生DFE信号的延迟采样,而第二路径产生来自延迟采样的DFE输出信号。

    SIGNAL ADJUSTMENT RECEIVER CIRCUITRY
    14.
    发明申请

    公开(公告)号:US20090284292A1

    公开(公告)日:2009-11-19

    申请号:US12511024

    申请日:2009-07-28

    IPC分类号: H03K5/12

    摘要: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

    Comparator offset cancellation assisted by PLD resources
    15.
    发明授权
    Comparator offset cancellation assisted by PLD resources 有权
    比较器偏移消除由PLD资源辅助

    公开(公告)号:US07541857B1

    公开(公告)日:2009-06-02

    申请号:US11323571

    申请日:2005-12-29

    IPC分类号: H03L5/00

    摘要: An impedance compensation circuit for inputs of a programmable device includes programmable impedance circuits connected with input nodes. The programmable impedance circuits can be configured to apply a compensating voltages to input nodes to reduce or eliminate unwanted offset voltages. An impedance compensation circuit may include resistors in series or current sources in parallel. A set of bypass switches selectively apply each resistor or current source to an input node, thereby changing the offset voltage of the node and compensating for impedance mismatches. Control logic provides signals to control the bypass switches. The control logic may be implemented using programmable device resources, enabling the control logic to be updated and improved after the manufacturing of the device is complete. The control logic can automatically evaluate offset voltages at any time and change compensating impedances accordingly. This reduces manufacturing costs and takes into account temperature and aging effects.

    摘要翻译: 用于可编程器件的输入的阻抗补偿电路包括与输入节点连接的可编程阻抗电路。 可编程阻抗电路可以配置为向输入节点施加补偿电压以减少或消除不期望的失调电压。 阻抗补偿电路可以包括并联的串联或电流源的电阻器。 一组旁路开关选择性地将每个电阻器或电流源施加到输入节点,从而改变节点的偏移电压并补偿阻抗失配。 控制逻辑提供信号来控制旁路开关。 可以使用可编程设备资源实现控制逻辑,使得在设备的制造完成之后能够更新和改进控制逻辑。 控制逻辑可以随时自动评估偏移电压,并相应地改变补偿阻抗。 这降低了制造成本并考虑了温度和老化的影响。

    Method and apparatus for standby voltage offset cancellation
    17.
    发明授权
    Method and apparatus for standby voltage offset cancellation 失效
    待机电压失调消除的方法和装置

    公开(公告)号:US08098087B1

    公开(公告)日:2012-01-17

    申请号:US11682282

    申请日:2007-03-05

    IPC分类号: H03K5/08

    CPC分类号: H04L25/03878 H03K5/249

    摘要: A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.

    摘要翻译: 提供了一种方法和装置,用于在接收器通道内的比较器的输入处的待机电压偏移消除。 第一比较器输入和第二比较器输入中的每一个与输入信号隔离,使得第一和第二比较器输入中的每一个达到相应的待机电压电平。 在第一和第二比较器输入之一上的电压电平递增地改变,同时监视比较器的输出信号。 在检测到比较器的输出信号中的状态转变时,一个比较器输入端的电压电平的增量变化在最终电压电平设置下停止。 最后的电压电平设置存储在计算机存储器中,用于参考在一个比较器输入处的电压电平的设置,以便补偿在比较器的输入处的待机电压偏移。

    Signal adjustment receiver circuitry
    18.
    发明授权
    Signal adjustment receiver circuitry 有权
    信号调节接收器电路

    公开(公告)号:US07733997B2

    公开(公告)日:2010-06-08

    申请号:US11486581

    申请日:2006-07-14

    IPC分类号: H04B1/10

    摘要: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies. For low frequency adjustment, user-programmable parameters control the normalized signal amplitude in the signal normalization block and the low frequency adjustment in the equalization block.

    摘要翻译: 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块,提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中,控制块控制用于高频的均衡块中的频率调整。 对于低频调整,用户可编程参数控制信号归一化块中的归一化信号幅度和均衡块中的低频调整。

    Signal adjustment receiver circuitry
    19.
    发明授权
    Signal adjustment receiver circuitry 有权
    信号调节接收器电路

    公开(公告)号:US07590174B2

    公开(公告)日:2009-09-15

    申请号:US11312181

    申请日:2005-12-20

    IPC分类号: H03H7/30 H03H7/40 H03K5/159

    摘要: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

    摘要翻译: 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块,提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中,控制块控制用于高频而不是低频的均衡块中的频率调整。 对于低频调整,控制块控制信号归一化块中的归一化信号幅度。 以这种方式,在信号归一化块中执行低频内容的受控调整。

    Digital adaptation circuitry and methods for programmable logic devices
    20.
    发明申请
    Digital adaptation circuitry and methods for programmable logic devices 有权
    用于可编程逻辑器件的数字适配电路和方法

    公开(公告)号:US20080069276A1

    公开(公告)日:2008-03-20

    申请号:US11522284

    申请日:2006-09-14

    IPC分类号: H04B1/10

    CPC分类号: H04L25/03885

    摘要: Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

    摘要翻译: 输入数据信号的均衡可以通过在该信号中的数据值应当稳定(“数据采样”)的时候对该信号进行采样来控制,并且当该信号应该在不同的连续数据值(“转换样本” )。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值(可以是这两个数据样本之一)进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。