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公开(公告)号：US08264214B1
公开(公告)日：2012-09-11
申请号：US13051648
申请日：2011-03-18
申请人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
发明人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.
摘要翻译： 低压参考电路可以具有一对半导体器件。 每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。 金属栅极可以具有与p型多晶硅相匹配的功函数。 栅极绝缘体可以具有小于约25埃的厚度。 金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。 第二端子可以接地。 偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。
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公开(公告)号：US08120429B1
公开(公告)日：2012-02-21
申请号：US12787722
申请日：2010-05-26
申请人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
发明人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
CPC分类号： H03L7/0995 , H03K3/0322 , H03K3/35613 , H03K2005/00228 , H03K2005/00234
摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.
摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。
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公开(公告)号：US07638990B1
公开(公告)日：2009-12-29
申请号：US11754295
申请日：2007-05-27
CPC分类号： G05F1/56
摘要： A power management system on an integrated circuit can include a first switch and a second switch. A regulator circuit provides current from a first supply voltage to a circuit block when the first switch is closed. The second switch provides current from a second supply voltage to the circuit block when the second switch is closed.
摘要翻译： 集成电路上的电源管理系统可以包括第一开关和第二开关。 当第一开关闭合时，调节器电路将电流从第一电源电压提供给电路块。 当第二开关闭合时，第二开关将电流从第二电源电压提供给电路块。
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4.发明授权Signal amplitude detection circuitry without pattern dependencies for high-speed serial links 有权信号幅度检测电路，无高速串行链路的模式相关性公开(公告)号：US07576570B1
公开(公告)日：2009-08-18
申请号：US11508607
申请日：2006-08-22
IPC分类号： H03K5/153
摘要： Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.
摘要翻译： 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。
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公开(公告)号：US07855576B1
公开(公告)日：2010-12-21
申请号：US11407444
申请日：2006-04-19
申请人： Mei Luo , Sergey Shumarayev , Thungoc M. Tran , Simardeep Maangat
发明人： Mei Luo , Sergey Shumarayev , Thungoc M. Tran , Simardeep Maangat
IPC分类号： H03K19/0175 , H03K19/003
CPC分类号： H03K19/017509 , H04L25/0276
摘要： Methods and apparatus are provided for selectively setting a CM voltage for a transceiver, reducing the effect of current mismatch, and generating a voltage step that can be used for receiver detection. A circuit of the invention can include voltage generator circuitry operable to generate a plurality of voltage signals of substantially different voltages. The circuit can also include multiplexer circuitry with voltage inputs coupled to the voltage signals. The multiplexer circuitry can be operable to select a reference signal from among the voltage inputs. In addition, the circuit can include operational amplifier (“op-amp”) circuitry with a first input coupled to the reference signal and a second input coupled to an output signal of the op-amp circuitry.
摘要翻译： 提供了用于选择性地设置收发器的CM电压的方法和装置，减少电流失配的影响，以及产生可用于接收机检测的电压步骤。 本发明的电路可以包括可操作以产生具有实质上不同电压的多个电压信号的电压发生器电路。 电路还可以包括具有耦合到电压信号的电压输入的多路复用器电路。 多路复用器电路可以用于从电压输入中选择参考信号。 此外，电路可以包括运算放大器（“运算放大器”）电路，其中耦合到参考信号的第一输入和耦合到运放电路的输出信号的第二输入。
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6.发明授权Increased sensitivity and reduced offset variation in high data rate HSSI receiver 有权在高数据速率HSSI接收机中增加灵敏度和减少偏移变化公开(公告)号：US07777526B2
公开(公告)日：2010-08-17
申请号：US12134777
申请日：2008-06-06
IPC分类号： H03K19/094
CPC分类号： H03K19/018514 , H03F3/45197 , H03F2203/45494 , H03F2203/45686
摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.
摘要翻译： 集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。 在一个实施例中，缓冲电路具有可变值电路元件。 进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。 在另一个实施例中，多级缓冲器的每个放大级提供可变增益。 级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。 在级联开始时也可以提供一个额外的前级放大器级。
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公开(公告)号：US07697600B2
公开(公告)日：2010-04-13
申请号：US11182658
申请日：2005-07-14
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.
摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。
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公开(公告)号：US20070014344A1
公开(公告)日：2007-01-18
申请号：US11182658
申请日：2005-07-14
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.
摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。
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公开(公告)号：US07154324B1
公开(公告)日：2006-12-26
申请号：US10935867
申请日：2004-09-07
IPC分类号： H03H3/26
CPC分类号： H03K5/133 , H03K2005/00039 , H03K2005/00058 , H03K2005/00143
摘要： Delay chain circuitry is provided. The delay chain circuitry has a number of delay chain inverters. Each delay chain inverter is connected in series with a load resistor and has an associated capacitor between its input and ground. The electrodes of each capacitor may be formed from metal separated by non-gate-oxide dielectric to maintain accurate capacitor tolerances. A stable current source such as a bandgap reference current source may apply a current to a sensing resistor. The resulting bias voltage is indicative of changes in resistance due to changes in operating temperature. A temperature compensation circuit may use the bias voltage to produce temperature-compensation control signals. The temperature-compensation control signals are applied to the delay chain inverters to adjust their resistances and compensate for temperature-induced changes in the resistances of the load resistors. This ensures that the delay of the delay chain is independent of operating temperature.
摘要翻译： 提供延迟链电路。 延迟链电路具有多个延迟链逆变器。 每个延迟链逆变器与负载电阻串联连接，并在其输入和地之间具有相关的电容器。 每个电容器的电极可以由由非栅极 - 氧化物电介质分离的金属形成，以保持精确的电容器公差。 诸如带隙参考电流源的稳定电流源可以向感测电阻器施加电流。 所产生的偏置电压表示由于工作温度变化引起的电阻变化。 温度补偿电路可以使用偏置电压来产生温度补偿控制信号。 温度补偿控制信号被施加到延迟链逆变器以调整其电阻并补偿负载电阻器的电阻的温度引起的变化。 这确保延迟链的延迟与工作温度无关。
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公开(公告)号：US08417752B1
公开(公告)日：2013-04-09
申请号：US12470254
申请日：2009-05-21
CPC分类号： H04B3/04
摘要： An equalizer circuitry that includes an equalizer stage having a programmable current source is described. In one implementation, the programmable current source cancels voltage offset. Also, in one implementation, the programmable current source is programmable in user mode. Furthermore, in one implementation, the equalizer circuitry includes a plurality of equalizer stages including the equalizer stage having a programmable current source, where the equalizer stage having a programmable current source is a second equalizer stage in the plurality of equalizer stages. Also, in one implementation, the programmable current source includes a plurality of current sources coupled in parallel and a plurality of sets of control switches for controlling the plurality of current sources. Further, in one implementation, each current source of the plurality of current sources includes a transistor and each set of control switches of the plurality of sets of control switches is for controlling a respective current source and includes a pair of transistors for controlling the respective current source.
摘要翻译： 描述了包括具有可编程电流源的均衡器级的均衡器电路。 在一个实现中，可编程电流源消除电压偏移。 而且，在一个实现中，可编程电流源可在用户模式下编程。 此外，在一个实现中，均衡器电路包括多个均衡器级，包括具有可编程电流源的均衡器级，其中具有可编程电流源的均衡器级是多个均衡器级中的第二均衡器级。 而且，在一个实现中，可编程电流源包括并联耦合的多个电流源和用于控制多个电流源的多组控制开关。 此外，在一个实现中，多个电流源的每个电流源包括晶体管，并且多组控制开关中的每组控制开关用于控制相应的电流源，并且包括用于控制相应电流的一对晶体管 资源。
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