公开(公告)号：US08098087B1

公开(公告)日：2012-01-17

申请号：US11682282

申请日：2007-03-05

申请人： John Dung-Ngoc Lam ,  Arch Zaliznyak ,  Wilson Wong ,  Tin H. Lai ,  Chong H. Lee ,  Sergey Shumarayev

发明人： John Dung-Ngoc Lam ,  Arch Zaliznyak ,  Wilson Wong ,  Tin H. Lai ,  Chong H. Lee ,  Sergey Shumarayev

IPC分类号： H03K5/08

CPC分类号： H04L25/03878 ,  H03K5/249

摘要： A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.

摘要翻译： 提供了一种方法和装置，用于在接收器通道内的比较器的输入处的待机电压偏移消除。 第一比较器输入和第二比较器输入中的每一个与输入信号隔离，使得第一和第二比较器输入中的每一个达到相应的待机电压电平。 在第一和第二比较器输入之一上的电压电平递增地改变，同时监视比较器的输出信号。 在检测到比较器的输出信号中的状态转变时，一个比较器输入端的电压电平的增量变化在最终电压电平设置下停止。 最后的电压电平设置存储在计算机存储器中，用于参考在一个比较器输入处的电压电平的设置，以便补偿在比较器的输入处的待机电压偏移。

公开(公告)号：US07675326B1

公开(公告)日：2010-03-09

申请号：US12163709

申请日：2008-06-27

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

公开(公告)号：US07940814B2

公开(公告)日：2011-05-10

申请号：US12576507

申请日：2009-10-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： H04J3/04

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US20110211621A1

公开(公告)日：2011-09-01

申请号：US13103132

申请日：2011-05-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： H04L5/14 ,  H04L27/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US07397270B1

公开(公告)日：2008-07-08

申请号：US11138919

申请日：2005-05-25

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

公开(公告)号：US06943588B1

公开(公告)日：2005-09-13

申请号：US10670146

申请日：2003-09-24

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

公开(公告)号：US08787352B2

公开(公告)日：2014-07-22

申请号：US13103132

申请日：2011-05-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： H04L12/28 ,  H04L5/14 ,  H04L27/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US20100058099A1

公开(公告)日：2010-03-04

申请号：US12576507

申请日：2009-10-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： G06F1/04 ,  G06F1/12

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US08949493B1

公开(公告)日：2015-02-03

申请号：US12847761

申请日：2010-07-30

申请人： Curt Wortman ,  Chong H. Lee ,  Huy Ngo

发明人： Curt Wortman ,  Chong H. Lee ,  Huy Ngo

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F5/00 ,  G06F13/12 ,  G06M3/00 ,  G11C19/00 ,  G01R31/28 ,  G06F17/50 ,  G06F1/02 ,  G06F7/58 ,  H04L9/00

CPC分类号： H04L25/03866 ,  G06F3/00 ,  G06F5/00 ,  G06F7/58 ,  G06F13/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/4221 ,  G06F13/4282 ,  G11C7/1012 ,  G11C7/1036 ,  G11C19/00 ,  G11C19/285 ,  H04L9/00

摘要： Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

摘要翻译： 公开了与可配置加扰电路相关的各种结构和方法。 实施例可以被配置为支持多个协议中的一个。 一些实施例涉及可配置的多径扰频器，其可以适于组合跨越多个车道的加扰电路或者提供独立的基于车道的加扰器。 一些实施例可配置为选择加扰器类型。 一些实施例可配置为适应多个协议特定的加扰多项式之一。 一些实施例涉及在数据的最低有效位（“LSB”）和最高有效位（“MSB”）排序之间进行选择。 在一些实施例中，每个通道中的加扰器电路适于处理超过一位宽的数据。

公开(公告)号：US08462908B2

公开(公告)日：2013-06-11

申请号：US12974949

申请日：2010-12-21

申请人： Ramanand Venkata ,  Chong H. Lee

发明人： Ramanand Venkata ,  Chong H. Lee

IPC分类号： H03D3/24

CPC分类号： H03M9/00 ,  H03L7/089 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0337

摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

摘要翻译： 锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。 候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。 出于同样的原因，发射侧可能会使用过量传输或过采样。