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    Half-rate DFE with duplicate path for high data-rate operation
    1.
    发明授权
    Half-rate DFE with duplicate path for high data-rate operation 有权
    具有高数据速率操作的重复路径的半速率DFE

    公开(公告)号：US07782935B1

    公开(公告)日：2010-08-24

    申请号：US11514490

    申请日：2006-08-31

    申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

    发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

    IPC分类号： H03H7/30

    CPC分类号： H03H11/26 ,  H04L25/03878 ,  H04L2025/0349

    摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.

    摘要翻译： 提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。 半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。 可以使用以输入信号数据速率的一半工作的两个延迟链电路。 更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。 多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。 重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。 第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

    Digital adaptation circuitry and methods for programmable logic devices
    2.
    发明授权
    Digital adaptation circuitry and methods for programmable logic devices 有权
    用于可编程逻辑器件的数字适配电路和方法

    公开(公告)号：US07920621B2

    公开(公告)日：2011-04-05

    申请号：US11522284

    申请日：2006-09-14

    申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885

    摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

    摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

    Digital adaptation circuitry and methods for programmable logic devices
    3.
    发明授权
    Digital adaptation circuitry and methods for programmable logic devices 有权
    用于可编程逻辑器件的数字适配电路和方法

    公开(公告)号：US08208523B2

    公开(公告)日：2012-06-26

    申请号：US13079420

    申请日：2011-04-04

    申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885

    摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

    摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

    DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
    4.
    发明申请
    DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
    数字适配​​电路和可编程逻辑器件的方法

    公开(公告)号：US20110188564A1

    公开(公告)日：2011-08-04

    申请号：US13079420

    申请日：2011-04-04

    申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    IPC分类号： H03K5/125 ,  H03K5/19

    CPC分类号： H04L25/03885

    摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

    摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

    Digital adaptation circuitry and methods for programmable logic devices
    5.
    发明申请
    Digital adaptation circuitry and methods for programmable logic devices 有权
    用于可编程逻辑器件的数字适配电路和方法

    公开(公告)号：US20080069276A1

    公开(公告)日：2008-03-20

    申请号：US11522284

    申请日：2006-09-14

    申请人： Wilson Wong ,  Doris Po Ching Chan ,  Simardeep Maangat ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    发明人： Wilson Wong ,  Doris Po Ching Chan ,  Simardeep Maangat ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    IPC分类号： H04B1/10

    CPC分类号： H04L25/03885

    摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

    摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

    Signal amplitude detection circuitry without pattern dependencies for high-speed serial links
    6.
    发明授权
    Signal amplitude detection circuitry without pattern dependencies for high-speed serial links 有权
    信号幅度检测电路，无高速串行链路的模式相关性

    公开(公告)号：US07576570B1

    公开(公告)日：2009-08-18

    申请号：US11508607

    申请日：2006-08-22

    申请人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H03K5/153

    CPC分类号： H03K5/153 ,  H03K5/24

    摘要： Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.

    摘要翻译： 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。

    Systems and methods for offset cancellation in integrated transceivers
    7.
    发明授权
    Systems and methods for offset cancellation in integrated transceivers 有权
    集成收发器偏移消除的系统和方法

    公开(公告)号：US07586983B1

    公开(公告)日：2009-09-08

    申请号：US11510446

    申请日：2006-08-24

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H03K5/159 ,  H04B1/10

    CPC分类号： H04L25/03057

    摘要： In high speed receiver circuitry (e.g., on a programmable logic device (PLD) or the like), decision feedback equalization (DFE) circuitry is used to at least partly cancel unwanted offset (e.g., from other elements of the receiver). The data input to the receiver is tristated; and then each DFE tap coefficient is varied in turn to find coefficient values that are associated with transitions between oscillation and non-oscillation of the receiver output signal. The coefficient values found in this way are used to select trial values. If the output signal of the receiver does not oscillate when these trial values are used, the process is repeated starting from these (or subsequent) trial values until a final set of trial values does allow oscillation of the receiver output signal.

    摘要翻译： 在高速接收机电路（例如，在可编程逻辑器件（PLD）等上）中，使用判决反馈均衡（DFE）电路来至少部分地消除不期望的偏移（例如，从接收机的其他元件）。 输入到接收机的数据被三态化; 然后依次改变每个DFE抽头系数，以找到与接收机输出信号的振荡和非振荡之间的转换相关联的系数值。 以这种方式找到的系数值用于选择试验值。 如果接收机的输出信号在使用这些试验值时不振荡，则从这些（或后续）试验值开始重复该过程，直到最终的试验值确定允许接收器输出信号的振荡。

    Decision feedback equalization for variable input amplitude
    9.
    发明授权
    Decision feedback equalization for variable input amplitude 有权
    用于可变输入幅度的判决反馈均衡

    公开(公告)号：US08416845B1

    公开(公告)日：2013-04-09

    申请号：US11484285

    申请日：2006-07-11

    申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

    发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H04L25/03057 ,  H03K5/1532

    摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.

    摘要翻译： 提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。 方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。 均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。 抽头系数可以由均衡电路自动调整。

    Wide range and dynamically reconfigurable clock data recovery architecture
    10.
    发明授权
    Wide range and dynamically reconfigurable clock data recovery architecture 有权
    宽范围和动态可重构的时钟数据恢复架构

    公开(公告)号：US08189729B2

    公开(公告)日：2012-05-29

    申请号：US11329197

    申请日：2006-01-09

    申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

    发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

    IPC分类号： H04L7/00

    CPC分类号： H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

    摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.

    摘要翻译： 宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 可以在不关闭电路或PLD的情况下动态重新编程参数。 这允许CDR电路在各种标准和协议之间进行即时切换。