Reduce line end pull back by exposing and etching space after mask one trim and etch
    11.
    发明授权
    Reduce line end pull back by exposing and etching space after mask one trim and etch 有权
    通过在掩模一次修整和蚀刻后曝光和蚀刻空间来减少线端拉回

    公开(公告)号:US07015148B1

    公开(公告)日:2006-03-21

    申请号:US10852883

    申请日:2004-05-25

    IPC分类号: H01L21/302 H01L21/461

    摘要: The invention is a method of manufacturing a semiconductor device and such semiconductor device. The semiconductor device includes an integrated circuit pattern including a horizontal line, a vertical line and a space therebetween, the space including a precise width dimension. The method includes the steps of: forming a photosensitive layer to be patterned, patterning the photosensitive layer to form a pattern including a master horizontal line and a master vertical line without a space therebetween, transferring the pattern to at least one underlying layer using the patterned photosensitive layer, forming a second photosensitive layer over the patterned at least one underlying layer, patterning the second photosensitive layer to form a second pattern including a master space aligned to dissect a horizontal line and a vertical line formed in the at least one underlying layer, and transferring the second pattern to the at least one underlying layer to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a precise width dimension.

    摘要翻译: 本发明是制造半导体器件和这种半导体器件的方法。 半导体器件包括集成电路图案,其包括水平线,垂直线和它们之间的空间,该空间包括精确的宽度尺寸。 该方法包括以下步骤:形成待图案化的感光层,图案化感光层以形成包括主水平线和主垂直线的图案,其间没有间隙,使用图案化将图案转移到至少一个下层 在所述图案化的至少一个下层上形成第二感光层,对所述第二感光层进行图案化,以形成第二图案,所述第二图案包括对准以剖开在所述至少一个下层中形成的水​​平线和垂直线的主空间, 以及将所述第二图案转移到所述至少一个下层,以形成包括水平线和在其间具有空间的垂直线的第三图案,所述空间包括精确的宽度尺寸。

    Method of lithographic mask correction using localized transmission adjustment
    12.
    发明授权
    Method of lithographic mask correction using localized transmission adjustment 有权
    使用局部传输调整的光刻掩模校正方法

    公开(公告)号:US08124300B1

    公开(公告)日:2012-02-28

    申请号:US10999404

    申请日:2004-11-30

    IPC分类号: G03F1/00

    CPC分类号: G03F1/32 G03F1/72

    摘要: A method of correcting a lithographic mask is disclosed. The method can include detecting a location of the mask that corresponds to a wafer location having a structure that is printed with a larger than desired dimension and reducing a thickness of at least a portion of a mask feature corresponding to the wafer structure to locally increase transmissivity of the mask feature.

    摘要翻译: 公开了一种校正光刻掩模的方法。 该方法可以包括检测对应于具有以大于期望尺寸印刷的结构的晶片位置的掩模的位置,并且减小对应于晶片结构的掩模特征的至少一部分的厚度以局部增加透射率 的面具功能。

    METHOD AND APPARATUS FOR MONITORING OPTICAL PROXIMITY CORRECTION PERFORMANCE
    13.
    发明申请
    METHOD AND APPARATUS FOR MONITORING OPTICAL PROXIMITY CORRECTION PERFORMANCE 审中-公开
    用于监测光学近似校正性能的方法和装置

    公开(公告)号:US20090144692A1

    公开(公告)日:2009-06-04

    申请号:US11948151

    申请日:2007-11-30

    IPC分类号: G06F17/50

    CPC分类号: G03F1/36 G03F1/68

    摘要: A method includes specifying a plurality of optical proximity correction metrology sites on a wafer. Metrology data is collected from at least a subset of the metrology sites. Data values are predicted for the subset of the metrology sites using an optical proximity correction design model. The collected metrology data is compared to the predicted data values to generate an optical proximity correction metric. A problem condition associated with the optical proximity correction design model is identified based on the optical proximity correction metric.

    摘要翻译: 一种方法包括在晶片上指定多个光学邻近校正度量位置。 计量学数据是从至少一个计量站点子集收集的。 使用光学邻近校正设计模型为量测站点的子集预测数据值。 将收集的测量数据与预测的数据值进行比较以产生光学邻近度校正度量。 基于光学邻近度校正度量来识别与光学接近校正设计模型相关联的问题状况。

    Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures
    14.
    发明授权
    Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures 失效
    使用在线编程的LER和可靠性结构提取工具独立的线边粗糙度(LER)测量

    公开(公告)号:US07310155B1

    公开(公告)日:2007-12-18

    申请号:US10958149

    申请日:2004-10-04

    IPC分类号: G01B11/04 G01B11/14

    摘要: A system that facilitates extraction of line edge roughness measurements that are independent of proprietorship of a metrology device comprises a structure patterned onto silicon with known line edge roughness values associated therewith. A metrology device obtains line edge roughness measurements from the structure, and a correcting component generates an inverse function based upon a comparison between the known line edge roughness values and the measured line edge roughness values. The metrology device can thereafter measure line edge roughness upon a second structure patterned on the silicon, and the inverse function can be applied to such measured line edge roughness values to enable obtainment of line edge roughness measurements that are independent of proprietorship of the metrology device.

    摘要翻译: 有助于提取独立于计量装置所有权的线边缘粗糙度测量的系统包括利用与其相关联的已知线边缘粗糙度值图案化到硅上的结构。 测量装置从该结构获得线边缘粗糙度测量,并且校正部件基于已知的线边缘粗糙度值与所测量的线边缘粗糙度值之间的比较产生反向函数。 测量装置此后可以在硅上图案化的第二结构上测量线边缘粗糙度,并且可以将反函数应用于这种测量的线边缘粗糙度值,以使得能够获得独立于计量装置所有权的线边缘粗糙度测量。

    Method for manufacturing place & route based on 2-D forbidden patterns
    15.
    发明授权
    Method for manufacturing place & route based on 2-D forbidden patterns 有权
    基于2-D禁止模式制造场所和路线的方法

    公开(公告)号:US07305645B1

    公开(公告)日:2007-12-04

    申请号:US10935488

    申请日:2004-09-07

    IPC分类号: G06F17/50 G06K9/00

    摘要: The present invention is directed towards a system and/or methodology that facilitates controlling routing of blocks on a floor plan in an integrated circuit. A pattern collector receives a partially created routing pattern, and a comparing component makes a comparison between the at least partially created routing pattern with one or more patterns in a library of patterns. Routing is controlled based at least in part upon the comparison.

    摘要翻译: 本发明涉及一种便于控制集成电路中的平面图上的块的路由的系统和/或方法。 模式收集器接收部分创建的路由模式,并且比较组件在至少部分创建的路由模式与模式库中的一个或多个模式之间进行比较。 至少部分地基于比较来控制路由。

    Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion
    16.
    发明授权
    Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion 失效
    通过四维空间分析和/或小波变换扩展来表征和合成OPC结构

    公开(公告)号:US06492066B1

    公开(公告)日:2002-12-10

    申请号:US09321089

    申请日:1999-05-28

    IPC分类号: G03F900

    CPC分类号: G03F1/36

    摘要: A method (100) of characterizing optical proximity correction designs includes performing a mathematical transform (160) on a first feature (150) and a second feature (167) each having a core portion (152) and a first OPC design and a second OPC design applied thereto, respectively. The method (100) further includes obtaining a metric (162) for the transformed first and second features, wherein the metric is based upon a capability of a pattern transfer system which will utilize masks employing the first and second features (150, 167) as a patterns thereon. One of the first feature or the second feature is then selected (170) based upon an application of the metric to the first and second transformed features (150, 167), thereby selecting the one of the first feature or the second feature which provides for a better pattern transfer performance.

    摘要翻译: 表征光学邻近校正设计的方法(100)包括在第一特征(150)和第二特征(167)上执行数学变换(160)和第二特征(167),每个具有核心部分(152)和第一OPC设计和第二OPC 分别设计了其设计。 方法(100)还包括获得用于变换的第一和第二特征的度量(162),其中度量基于模式传送系统的能力,其将利用采用第一和第二特征(150,167)的掩模作为 其上的图案。 然后基于将度量应用于第一和第二变换特征(150,167)来选择第一特征或第二特征之一(170),从而选择第一特征或第二特征中的一个,其提供 更好的图案转移性能。

    Mask quality measurements by fourier space analysis
    17.
    发明授权
    Mask quality measurements by fourier space analysis 有权
    面罩质量测量通过四维空间分析

    公开(公告)号:US06187483B1

    公开(公告)日:2001-02-13

    申请号:US09322546

    申请日:1999-05-28

    IPC分类号: G03F900

    CPC分类号: G03F1/36

    摘要: A method (200) of determining an optimal mask fabrication process includes fabricating (202) a first mask pattern (220) on a mask using a first mask fabrication process and a second mask pattern (222) on a mask using a second mask fabrication process, wherein each mask pattern approximates an ideal pattern. The method (200) further includes performing a mathematical transform on the first and second mask patterns (230), wherein the mathematical transform provides a representation of the first and second mask patterns as sums of functions. A metric is then obtained for the transformed mask patterns (220, 222), wherein the metric is based upon a capability of a pattern transfer system which will utilize the masks employing the first and second mask patterns one of the first and second mask fabrication processes is selected (236) based upon an application of the metric to the first and second sum of orthogonal functions, thereby selecting the one of the first or second mask fabrication processes that provides for a better mask pattern which most closely approximates the ideal mask pattern.

    摘要翻译: 确定最佳掩模制造工艺的方法(200)包括使用第二掩模制造工艺在掩模上使用第一掩模制造工艺和掩模图案(222)在掩模上制造(202)第一掩模图案(220) ,其中每个掩模图案接近理想图案。 方法(200)还包括对第一和第二掩模图案(230)执行数学变换,其中数学变换提供第一和第二掩模图案的表示作为函数的和。 然后获得用于变换的掩模图案(220,222)的度量,其中度量基于图案传送系统的能力,该图案传送系统将利用采用第一和第二掩模图案的掩模,第一和第二掩模制造工艺之一 被选择(236),其基于对第一和第二正交函数之和的度量的应用,从而选择提供最接近理想掩模图案的更好的掩模图案的第一或第二掩模制造工艺中的一个。

    METHOD AND APPARATUS FOR MONITORING MARGINAL LAYOUT DESIGN RULES
    18.
    发明申请
    METHOD AND APPARATUS FOR MONITORING MARGINAL LAYOUT DESIGN RULES 审中-公开
    用于监测标准布局设计规则的方法和装置

    公开(公告)号:US20090144686A1

    公开(公告)日:2009-06-04

    申请号:US11948218

    申请日:2007-11-30

    IPC分类号: G06F19/00

    CPC分类号: G06F17/5081

    摘要: A method includes generating a layout for an integrated circuit device in accordance with a plurality of layout design rules. A plurality of metrology sites on the layout associated with at least one subset of the layout design rules is identified. A metrology tag associated with each of the metrology sites is generated. At least one metrology recipe for determining a characteristic of the integrated circuit device is generated based on the metrology tags. Metrology data is collected using the at least one metrology recipe. A selected layout design rule in the at least one subset is modified based on the metrology data.

    摘要翻译: 一种方法包括根据多个布局设计规则生成用于集成电路设备的布局。 识别与布局设计规则的至少一个子集相关联的布局上的多个计量站点。 生成与每个测量点相关联的度量标签。 基于计量标签生成至少一个用于确定集成电路装置的特性的计量配方。 使用至少一个计量学方法收集计量学数据。 基于测量数据修改至少一个子集中的选定的布局设计规则。

    Methods for pattern matching in a double patterning technology-compliant physical design flow
    19.
    发明授权
    Methods for pattern matching in a double patterning technology-compliant physical design flow 有权
    双图案技术兼容物理设计流程中模式匹配的方法

    公开(公告)号:US08418105B1

    公开(公告)日:2013-04-09

    申请号:US13349412

    申请日:2012-01-12

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.

    摘要翻译: 公开了一种用于制造集成电路的方法,其包括根据实施例,为集成电路提供绘制的布局逻辑设计,所述逻辑设计包括多个图案; 检查多种图案以进行双重图案化技术合规; 识别非双重图案化技术兼容图案; 提供用于替换所识别的非双图案化技术兼容图案的双重图案化技术兼容图案,由此创建经修改的逻辑设计; 生成实现修改后的逻辑设计的掩码集; 并且采用该掩模组来实现在半导体衬底中和之上的修改的逻辑设计。