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1.发明授权Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures 失效使用在线编程的LER和可靠性结构提取工具独立的线边粗糙度（LER）测量公开(公告)号：US07310155B1
公开(公告)日：2007-12-18
申请号：US10958149
申请日：2004-10-04
CPC分类号： G01B11/303 , G01N21/47 , G01N21/9501
摘要： A system that facilitates extraction of line edge roughness measurements that are independent of proprietorship of a metrology device comprises a structure patterned onto silicon with known line edge roughness values associated therewith. A metrology device obtains line edge roughness measurements from the structure, and a correcting component generates an inverse function based upon a comparison between the known line edge roughness values and the measured line edge roughness values. The metrology device can thereafter measure line edge roughness upon a second structure patterned on the silicon, and the inverse function can be applied to such measured line edge roughness values to enable obtainment of line edge roughness measurements that are independent of proprietorship of the metrology device.
摘要翻译： 有助于提取独立于计量装置所有权的线边缘粗糙度测量的系统包括利用与其相关联的已知线边缘粗糙度值图案化到硅上的结构。 测量装置从该结构获得线边缘粗糙度测量，并且校正部件基于已知的线边缘粗糙度值与所测量的线边缘粗糙度值之间的比较产生反向函数。 测量装置此后可以在硅上图案化的第二结构上测量线边缘粗糙度，并且可以将反函数应用于这种测量的线边缘粗糙度值，以使得能够获得独立于计量装置所有权的线边缘粗糙度测量。
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2.发明授权公开(公告)号：US07305645B1
公开(公告)日：2007-12-04
申请号：US10935488
申请日：2004-09-07
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： The present invention is directed towards a system and/or methodology that facilitates controlling routing of blocks on a floor plan in an integrated circuit. A pattern collector receives a partially created routing pattern, and a comparing component makes a comparison between the at least partially created routing pattern with one or more patterns in a library of patterns. Routing is controlled based at least in part upon the comparison.
摘要翻译： 本发明涉及一种便于控制集成电路中的平面图上的块的路由的系统和/或方法。 模式收集器接收部分创建的路由模式，并且比较组件在至少部分创建的路由模式与模式库中的一个或多个模式之间进行比较。 至少部分地基于比较来控制路由。
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3.发明授权公开(公告)号：US08124300B1
公开(公告)日：2012-02-28
申请号：US10999404
申请日：2004-11-30
申请人： Bhanwar Singh , Luigi Capodieci
发明人： Bhanwar Singh , Luigi Capodieci
IPC分类号： G03F1/00
摘要： A method of correcting a lithographic mask is disclosed. The method can include detecting a location of the mask that corresponds to a wafer location having a structure that is printed with a larger than desired dimension and reducing a thickness of at least a portion of a mask feature corresponding to the wafer structure to locally increase transmissivity of the mask feature.
摘要翻译： 公开了一种校正光刻掩模的方法。 该方法可以包括检测对应于具有以大于期望尺寸印刷的结构的晶片位置的掩模的位置，并且减小对应于晶片结构的掩模特征的至少一部分的厚度以局部增加透射率 的面具功能。
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4.发明申请METHOD AND APPARATUS FOR MONITORING OPTICAL PROXIMITY CORRECTION PERFORMANCE 审中-公开用于监测光学近似校正性能的方法和装置公开(公告)号：US20090144692A1
公开(公告)日：2009-06-04
申请号：US11948151
申请日：2007-11-30
IPC分类号： G06F17/50
摘要： A method includes specifying a plurality of optical proximity correction metrology sites on a wafer. Metrology data is collected from at least a subset of the metrology sites. Data values are predicted for the subset of the metrology sites using an optical proximity correction design model. The collected metrology data is compared to the predicted data values to generate an optical proximity correction metric. A problem condition associated with the optical proximity correction design model is identified based on the optical proximity correction metric.
摘要翻译： 一种方法包括在晶片上指定多个光学邻近校正度量位置。 计量学数据是从至少一个计量站点子集收集的。 使用光学邻近校正设计模型为量测站点的子集预测数据值。 将收集的测量数据与预测的数据值进行比较以产生光学邻近度校正度量。 基于光学邻近度校正度量来识别与光学接近校正设计模型相关联的问题状况。
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5.发明授权公开(公告)号：US06995433B1
公开(公告)日：2006-02-07
申请号：US10791250
申请日：2004-03-02
IPC分类号： H01L29/94 , H01L31/062
CPC分类号： H01L29/7835 , H01L21/32139 , H01L29/4238 , H01L29/66659
摘要： A microdevice for forming a part of an integrated circuit and method for fabricating are disclosed. The microdevice can include a first conductive region and a second conductive region having a channel region interposed therebetween. The mircodevice has a channel region controlling component disposed over the channel region and separated therefrom by at least one dielectric layer. The channel region controlling component has a non-linear structural characteristic derived from a non-linear structural characteristic of a photo resist feature used as an etch mask for the channel region controlling component.
摘要翻译： 公开了一种用于形成集成电路的一部分的微型器件及其制造方法。 微器件可以包括第一导电区域和介于其之间的沟道区域的第二导电区域。 微电极具有设置在沟道区域上并由至少一个电介质层分离的沟道区域控制部件。 通道区域控制部件具有从用作沟道区域控制部件的蚀刻掩模的光致抗蚀剂特征的非线性结构特性导出的非线性结构特性。
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6.发明授权Lithographic photomask and method of manufacture to improve photomask test measurement 失效平版印刷光掩模和制造方法以改进光掩模测试测量公开(公告)号：US06974652B1
公开(公告)日：2005-12-13
申请号：US10699748
申请日：2003-11-03
摘要： A photomask for use in a lithographic process and a method of making a photomask are disclosed. A mask blank including a substrate, a sacrificial conductive layer disposed over the substrate and a radiation shielding layer disposed over the sacrificial conductive layer can be provided. Structures are then formed from the radiation shielding layer to define a pattern. Measurement of parameters associated with the structures are made with a measurement tool and, during the measuring, the sacrificial conductive layer provides a conductive plane to dissipate charge transferred to the mask by the measurement tool.
摘要翻译： 公开了用于光刻工艺的光掩模和制造光掩模的方法。 可以提供包括衬底，设置在衬底上的牺牲导电层和设置在牺牲导电层上方的辐射屏蔽层的掩模坯料。 然后从辐射屏蔽层形成结构以限定图案。 使用测量工具测量与结构相关的参数，并且在测量期间，牺牲导电层提供导电平面以消散由测量工具传递到掩模的电荷。
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公开(公告)号：US20090144686A1
公开(公告)日：2009-06-04
申请号：US11948218
申请日：2007-11-30
IPC分类号： G06F19/00
CPC分类号： G06F17/5081
摘要： A method includes generating a layout for an integrated circuit device in accordance with a plurality of layout design rules. A plurality of metrology sites on the layout associated with at least one subset of the layout design rules is identified. A metrology tag associated with each of the metrology sites is generated. At least one metrology recipe for determining a characteristic of the integrated circuit device is generated based on the metrology tags. Metrology data is collected using the at least one metrology recipe. A selected layout design rule in the at least one subset is modified based on the metrology data.
摘要翻译： 一种方法包括根据多个布局设计规则生成用于集成电路设备的布局。 识别与布局设计规则的至少一个子集相关联的布局上的多个计量站点。 生成与每个测量点相关联的度量标签。 基于计量标签生成至少一个用于确定集成电路装置的特性的计量配方。 使用至少一个计量学方法收集计量学数据。 基于测量数据修改至少一个子集中的选定的布局设计规则。
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8.发明授权Methods for pattern matching in a double patterning technology-compliant physical design flow 有权双图案技术兼容物理设计流程中模式匹配的方法公开(公告)号：US08418105B1
公开(公告)日：2013-04-09
申请号：US13349412
申请日：2012-01-12
申请人： Lynn T. Wang , Vito Dai , Luigi Capodieci
发明人： Lynn T. Wang , Vito Dai , Luigi Capodieci
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.
摘要翻译： 公开了一种用于制造集成电路的方法，其包括根据实施例，为集成电路提供绘制的布局逻辑设计，所述逻辑设计包括多个图案; 检查多种图案以进行双重图案化技术合规; 识别非双重图案化技术兼容图案; 提供用于替换所识别的非双图案化技术兼容图案的双重图案化技术兼容图案，由此创建经修改的逻辑设计; 生成实现修改后的逻辑设计的掩码集; 并且采用该掩模组来实现在半导体衬底中和之上的修改的逻辑设计。
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9.发明授权System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法公开(公告)号：US07269804B2
公开(公告)日：2007-09-11
申请号：US10816764
申请日：2004-04-02
申请人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
发明人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译： 选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。 对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。 可以选择提供最佳可制造性的RET。 以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。
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10.发明申请公开(公告)号：US20070209030A1
公开(公告)日：2007-09-06
申请号：US11741845
申请日：2007-04-30
申请人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
发明人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译： 选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。 对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。 可以选择提供最佳可制造性的RET。 以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。
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