公开(公告)号：US20230078381A1

公开(公告)日：2023-03-16

申请号：US17882229

申请日：2022-08-05

Applicant: Tokyo Electron Limited

Inventor： Lars LIEBMANN ,  Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Paul GUTWIN

IPC: H01L27/092 ,  H01L21/822 ,  H01L27/02

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.

公开(公告)号：US20220416048A1

公开(公告)日：2022-12-29

申请号：US17851975

申请日：2022-06-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Paul GUTWIN ,  Kandabara TAPILY ,  Subhadeep KAL ,  Robert CLARK

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

Abstract: Aspects of the present disclosure provide a method, which includes providing a semiconductor structure including a first lower semiconductor device and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first lower semiconductor device has one or more first lower channels. The first upper semiconductor device has one or more first upper channels. First work function metal (WFM) can cover the first lower channels and the first upper channels. The method can also include recessing the first WFM to uncover the first upper channels of the first upper semiconductor device, depositing a monolayer on uncovered dielectric surfaces of the semiconductor structure, depositing isolation dielectric on the first WFM of the first lower semiconductor device, and depositing second WFM to cover the first upper channels of the first upper semiconductor device. The isolation dielectric isolates the first lower semiconductor device from the first upper semiconductor device.

公开(公告)号：US20220223496A1

公开(公告)日：2022-07-14

申请号：US17344231

申请日：2021-06-10

Applicant: Tokyo Electron Limited

Inventor： Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Jeffrey SMITH ,  Paul GUTWIN

IPC: H01L23/473 ,  H01L21/8238 ,  H01L21/8234

Abstract: A microfabrication device is provided. The microfabrication device includes a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors; fluidic passages formed within the transistor plane; a dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the transistor plane.

公开(公告)号：US20220181322A1

公开(公告)日：2022-06-09

申请号：US17328446

申请日：2021-05-24

Applicant: Tokyo Electron Limited

Inventor： Lars LIEBMANN ,  Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Paul GUTWIN

IPC: H01L27/092 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786

Abstract: A semiconductor device includes a cell array having tracks and rows formed on a substrate. The tracks extend perpendicularly to the rows. A logic cell is formed across two adjacent rows within the cell array. The logic cell includes a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows. Each XC includes two cross-coupled complementary field-effect-transistors. Each poly track is configured to function as an inter-row gate for the XCs. A pair of signal tracks is positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks.