公开(公告)号：US20210118730A1

公开(公告)日：2021-04-22

申请号：US17135136

申请日：2020-12-28

Applicant: Tokyo Electron Limited

Inventor： Robert CLARK ,  Kndabara TAPILY ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418

Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

公开(公告)号：US20220416048A1

公开(公告)日：2022-12-29

申请号：US17851975

申请日：2022-06-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Paul GUTWIN ,  Kandabara TAPILY ,  Subhadeep KAL ,  Robert CLARK

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

Abstract: Aspects of the present disclosure provide a method, which includes providing a semiconductor structure including a first lower semiconductor device and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first lower semiconductor device has one or more first lower channels. The first upper semiconductor device has one or more first upper channels. First work function metal (WFM) can cover the first lower channels and the first upper channels. The method can also include recessing the first WFM to uncover the first upper channels of the first upper semiconductor device, depositing a monolayer on uncovered dielectric surfaces of the semiconductor structure, depositing isolation dielectric on the first WFM of the first lower semiconductor device, and depositing second WFM to cover the first upper channels of the first upper semiconductor device. The isolation dielectric isolates the first lower semiconductor device from the first upper semiconductor device.

公开(公告)号：US20220181176A1

公开(公告)日：2022-06-09

申请号：US17682202

申请日：2022-02-28

Applicant: Tokyo Electron Limited

Inventor： Robert CLARK ,  Kandabara TAPILY

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/311 ,  H01L21/02 ,  C23C16/06 ,  C23C16/40 ,  C23C16/02 ,  C23C16/56

Abstract: A substrate processing method includes (a) providing a substrate in a substrate processing tool, the substrate containing an exposed surface of a first material layer and an exposed surface of a second material layer; (b) forming a self-assembled monolayer (SAM) on the substrate in a first substrate processing chamber (SPC); (c) transferring the substrate from the first SPC through a substrate transfer chamber to a second SPC; (d) depositing a film selectively on the first material layer and film nuclei on the SAM in the second SPC; (e) transferring, after selectively depositing the film on the first material layer, the substrate from the second SPC through the substrate transfer chamber to a third SPC; (f) removing the film nuclei from the SAM by etching in the third SPC; and repeating (b), (c), (d), (e) and (f) sequentially at least once.

公开(公告)号：US20220122892A1

公开(公告)日：2022-04-21

申请号：US17392997

申请日：2021-08-03

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Paul GUTWIN ,  Robert CLARK ,  Anton DEVILLIERS

IPC: H01L21/8238 ,  H01L23/00 ,  H01L21/306 ,  H01L21/324

Abstract: Techniques herein include methods for fabricating CFET devices. The methods enable high-temperature processes to be performed for FINFET and gate all around (GAA) technologies without degradation of temperature sensitive materials within the device and transistors. In particular, high temperature anneals and depositions can be performed prior to deposition of temperature-sensitive materials, such as work function metals and silicides. The methods enable at least two transistor devices to be fabricated in a stepwise manner while preventing thermal violations of any materials in either transistor.

公开(公告)号：US20210125863A1

公开(公告)日：2021-04-29

申请号：US17140310

申请日：2021-01-04

Applicant: Tokyo Electron Limited

Inventor： Robert CLARK ,  Kandabara TAPILY ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418

Abstract: A method of preparing a self-aligned via on a semiconductor workpiece includes using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules. The integrated sequence of processing steps include receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface; selectively etching the metal features to form a recess pattern by recessing the exposed surfaces of the metal features beneath the exposed surfaces of the dielectric layer using one of the one or more etching modules; and depositing an etch stop layer over the recess pattern using one of the one or more film-forming modules.