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    INVERTED CROSS-COUPLE FOR TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3DI
    1.
    发明申请
    INVERTED CROSS-COUPLE FOR TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3DI 有权

    公开(公告)号：US20220367461A1

    公开(公告)日：2022-11-17

    申请号：US17737640

    申请日：2022-05-05

    Applicant: Tokyo Electron Limited

    Inventor： Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Jeffrey SMITH ,  Paul GUTWIN

    IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238

    Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    2.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230100332A1

    公开(公告)日：2023-03-30

    申请号：US18074684

    申请日：2022-12-05

    Applicant: Tokyo Electron Limited

    Inventor： Lars LIEBMANN ,  Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Paul GUTWIN

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

    Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.

    INDEPENDENT GATE CONTACTS FOR CFET
    3.
    发明申请
    INDEPENDENT GATE CONTACTS FOR CFET 有权

    公开(公告)号：US20230017350A1

    公开(公告)日：2023-01-19

    申请号：US17836019

    申请日：2022-06-09

    Applicant: Tokyo Electron Limited

    Inventor： Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Jeffrey SMITH ,  Paul GUTWIN

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L29/66

    Abstract: Aspects of the present disclosure provide a method of manufacturing a three-dimensional (3D) semiconductor device. For example, the method can include forming a target structure, the target structure including a lower gate region, an upper gate region, and a separation layer disposed between and separating the lower gate region and the upper gate region. The method can also include forming a sacrificial contact structure extending vertically from the bottom gate region through the separation layer and the upper gate region to a position above the upper gate region, removing at least a portion of the sacrificial contact structure resulting in a lower gate contact opening extending from the position above the upper gate region to the bottom gate region, insulating a side wall surface of the lower gate contact opening, and filling the lower gate contact opening with a conductor to form a lower gate contact.

    INTEGRATED HIGH EFFICIENCY GATE ON GATE COOLING
    5.
    发明申请
    INTEGRATED HIGH EFFICIENCY GATE ON GATE COOLING 有权

    公开(公告)号：US20220223497A1

    公开(公告)日：2022-07-14

    申请号：US17344259

    申请日：2021-06-10

    Applicant: Tokyo Electron Limited

    Inventor： Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Jeffrey SMITH ,  Paul GUTWIN

    IPC: H01L23/473 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A microfabrication device is provided. The microfabrication device includes a combined substrate including a first substrate connected to a second substrate, the first substrate having first devices and the second substrate having second devices; fluidic passages formed at a connection point between the first substrate and the second substrate, the connection point including a wiring structure that electrically connects first devices to second devices and physically connects the first substrate to the second substrate; dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the fluidic passages to transfer heat.

    THREE-DIMENSIONAL MEMORY CELL STRUCTURE
    8.
    发明申请
    THREE-DIMENSIONAL MEMORY CELL STRUCTURE 有权

    公开(公告)号：US20220302121A1

    公开(公告)日：2022-09-22

    申请号：US17644982

    申请日：2021-12-17

    Applicant: Tokyo Electron Limited

    Inventor： Paul GUTWIN ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME

    IPC: H01L27/108 ,  H01L27/11 ,  G11C11/412 ,  G11C11/402

    Abstract: In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.

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