公开(公告)号：US07535736B2

公开(公告)日：2009-05-19

申请号：US11763474

申请日：2007-06-15

申请人： Masaru Nakamura ,  Masaaki Shimada

发明人： Masaru Nakamura ,  Masaaki Shimada

IPC分类号： H02M3/335 ,  H02H7/122

CPC分类号： H02M3/33523 ,  H02M1/32

摘要： A switching power supply has a switching device connected via a primary winding of a transformer to DC input voltage; a circuit for rectifying voltage at a secondary winding of the transformer, and outputting an output signal; and a control circuit for controlling on/off states of the switching device. The control circuit detects a current signal generated based on a forward voltage generated at a drive winding of the transformer while the switching device is on; generates an input correction signal using the current signal, the level of the input correction signal varying in accordance with the DC input voltage; detects a signal of current flowing through the switching device; and compares the input correction signal with the signal of the current flowing through the switching device, and limits the maximum value of this current in accordance with the DC input voltage.

摘要翻译： 开关电源具有通过变压器的初级绕组连接到DC输入电压的开关装置; 用于对变压器的次级绕组进行整流电压的电路，并输出输出信号; 以及用于控制开关装置的导通/截止状态的控制电路。 控制电路根据在变压器的驱动绕组产生的正向电压而产生的电流信号，同时开关装置接通; 使用当前信号生成输入校正信号，输入校正信号的电平根据DC输入电压而变化; 检测流经切换装置的电流信号; 并将输入校正信号与流过开关器件的电流的信号进行比较，并根据直流输入电压限制该电流的最大值。

公开(公告)号：US20080293220A1

公开(公告)日：2008-11-27

申请号：US11889024

申请日：2007-08-08

申请人： Masaru Nakamura

发明人： Masaru Nakamura

IPC分类号： H01L21/302

CPC分类号： H01L21/78 ,  H01L21/67092 ,  H01L21/67132

摘要： A method of dividing a wafer having a plurality of dividing lines which are formed in a lattice pattern on the front surface, into individual chips along the dividing lines, the method comprising a wafer affixing step for affixing the front surface of the wafer to the front surface of a holding plate having stiffness through an adherent layer; a grinding step for grinding the rear surface of the wafer affixed to the holding plate to a predetermined thickness; a deteriorated layer forming step for applying a pulse laser beam of a wavelength having permeability for the wafer from the rear surface of the wafer which is affixed to the holding plate and has undergone the grinding step to form a deteriorated layer in the inside of the wafer along the dividing lines; a wafer transfer step for putting the rear surface of the wafer which has undergone the deteriorated layer forming step on an adherent tape mounted on an annular frame and removing the holding plate from the front surface of the wafer; and a wafer dividing step for exerting external force to the wafer put on the adherent tape to divide the wafer along the dividing lines.

摘要翻译： 一种将在前表面上以格子状形成的多条分割线的晶片沿分割线划分成各个芯片的方法，该方法包括将晶片的前表面固定在前面的晶片固定步骤 通过粘合层具有刚度的保持板的表面; 研磨步骤，用于将固定在所述保持板上的所述晶片的后表面研磨至预定厚度; 劣化层形成步骤，用于从固定在保持板上的晶片的背面施加具有晶片导磁率的波长的脉冲激光束，并进行研磨步骤，以在晶片内部形成劣化层 沿分界线; 用于将已经经历劣化层形成步骤的晶片的后表面放置在安装在环形框架上的粘附带上并从晶片的前表面移除保持板的晶片转移步骤; 以及用于对放置在粘附带上的晶片施加外力以沿分割线分割晶片的晶片分割步骤。

公开(公告)号：US07446930B2

公开(公告)日：2008-11-04

申请号：US10575271

申请日：2004-11-10

申请人： Kenji Kitamura ,  Sunao Kurimura ,  Masaru Nakamura ,  Shunji Takekawa ,  Kazuya Terabe ,  Shunichi Hishida ,  Tamaki Shimura

发明人： Kenji Kitamura ,  Sunao Kurimura ,  Masaru Nakamura ,  Shunji Takekawa ,  Kazuya Terabe ,  Shunichi Hishida ,  Tamaki Shimura

IPC分类号： G02F1/35 ,  G02F2/02

CPC分类号： G02F1/3558 ,  G02F2202/20

摘要： A problem to be solved is to provide a method of forming domain inverted regions of short period in a ferroelectric single crystal in a controllable time period of application of voltage and an optical wavelength conversion element using the same.A solving means of it solves the problem by forming (i) a control layer having a larger defect density Dcont1 than the defect density Dferro of a ferroelectric single crystal (Dferro

摘要翻译： 要解决的问题是提供一种在施加电压的可控时间内在铁电单晶中形成短周期的畴反转区域的方法和使用其的光波长转换元件。 其解决方法通过形成（i）具有比铁电单晶（D）的缺陷密度D 更大的缺陷密度D 的控制层来解决该问题 或者形成（ii）具有比铁电单晶的格点的次序小的点阵次数的控制层， 垂直于铁电单晶中的铁电单晶的偏振方向的面。

公开(公告)号：US20080153264A1

公开(公告)日：2008-06-26

申请号：US12071711

申请日：2008-02-25

申请人： Masaru Nakamura ,  Yusuke Nagai

发明人： Masaru Nakamura ,  Yusuke Nagai

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  B23K26/40 ,  B23K2103/50 ,  B28D5/0011 ,  H01L21/6836 ,  H01L2221/68327

摘要： A method of dividing a wafer having a plurality of devices, which are formed in a plurality of areas sectioned by streets formed in a lattice pattern on the front surface, and having test metal patterns which are formed on the streets, comprising the steps of: a laser beam application step for carrying out laser processing to form a dividing start point along a street on both sides of the test metal patterns by applying a laser beam along the street on both sides of the test metal patterns in the street formed on the wafer; and a dividing step for dividing the wafer which has been laser processed to form dividing start points along the dividing start points by exerting external force to the wafer, resulting in leaving the streets having the test metal patterns formed thereon behind.

摘要翻译： 一种分割具有多个装置的晶片的方法，所述晶片形成在由前表面上的格子图案形成的街道划分的多个区域中，并且具有形成在街道上的测试金属图案，包括以下步骤： 激光束施加步骤，用于通过在形成在晶片上的街道中的测试金属图案的两侧沿着街道施加激光束来进行激光处理以在测试金属图案的两侧上沿着街道形成分割起始点 ; 以及分割步骤，通过向晶片施加外力，分割已经被激光处理的晶片沿分割开始点形成分割开始点，导致留下在其上形成有测试金属图案的街道。

公开(公告)号：US07329564B2

公开(公告)日：2008-02-12

申请号：US11198137

申请日：2005-08-08

申请人： Masaru Nakamura ,  Yusuke Nagai ,  Kentaro Iizuka

发明人： Masaru Nakamura ,  Yusuke Nagai ,  Kentaro Iizuka

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L21/6836 ,  H01L21/78 ,  H01L33/0095 ,  H01L2221/68327 ,  H01L2221/68336

摘要： A method of dividing a wafer having a plurality of dividing lines formed on the front surface in a lattice pattern and function elements formed in a plurality of areas sectioned by the plurality of dividing lines into individual chips, along the dividing lines, the method comprising the steps of forming a deteriorated layer by applying a laser beam capable of passing through the wafer along the dividing lines; expanding the support tape affixed to the wafer to divide the wafer into individual chips along the dividing lines where the deteriorated layer has been formed and to form a space between adjacent chips; and applying an external stimulus to an area, to which the wafer is affixed, of the support tape in the above state to cure the adhesive layer to maintain the space between adjacent chips.

摘要翻译： 一种将沿着划分线将形成在前表面上的多个划分线的晶片和由多个分割线划分成多个区域的功能元件分成单个芯片的方法，该方法包括： 通过施加能够沿分割线穿过晶片的激光束形成劣化层的步骤; 扩展固定在晶片上的支撑胶带，沿着形成了劣化层的分割线将晶片分割成单独的芯片，并在相邻芯片之间形成空间; 并且在上述状态下将外部刺激施加到支撑带的晶片固定的区域上，以固化粘合剂层以保持相邻芯片之间的空间。

公开(公告)号：US07292461B2

公开(公告)日：2007-11-06

申请号：US11549850

申请日：2006-10-16

申请人： Masaru Nakamura

发明人： Masaru Nakamura

IPC分类号： H02M3/335

CPC分类号： H02M3/3385

摘要： A switching power source apparatus has a switching element being connected with a DC power source through a primary winding of a transformer in which parasitic capacitance exists between terminals of the switching element. A voltage V4 of free oscillation appears at a gate of the switching element after a flyback period due to the parasitic capacitance. Based on the free oscillation voltage, the switching power source apparatus detects timing synchronized with a period of the free oscillation, outputs a trigger signal V10 based on the detected timing, uses the trigger signal to estimate bottom timing when the free oscillation reaches a bottom level the second time, outputs an ON start signal V9 synchronized with the bottom timing, uses the ON start signal to output an ON control signal to turn on the switching element, and drives the switching element in response to the ON control signal.

摘要翻译： 开关电源装置具有通过变压器的初级绕组与直流电源连接的开关元件，其中开关元件的端子之间存在寄生电容。 在由于寄生电容引起的反激期之后，开关元件的栅极处出现自由振荡的电压V 4。 基于自由振荡电压，开关电源装置检测与自由振荡周期同步的定时，基于检测到的定时输出触发信号V10，当自由振荡达到底部时，使用触发信号来估计底部定时 输出与底部定时同步的ON启动信号V9，使用ON起始信号输出ON控制信号以接通开关元件，并响应于ON控制信号驱动开关元件。

公开(公告)号：US20070057378A1

公开(公告)日：2007-03-15

申请号：US11519321

申请日：2006-09-12

申请人： Kazuhisa Arai ,  Masaru Nakamura

发明人： Kazuhisa Arai ,  Masaru Nakamura

IPC分类号： H01L23/52

CPC分类号： H01L21/6835 ,  B23K26/40 ,  B23K26/50 ,  B23K26/53 ,  B23K2103/50 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512

摘要： On the back surface of the chip of which a front surface is formed with an electronic circuit, an adhesive film of a shape and dimensions corresponding to at least the back surface of the chip is adhered to obtain the semiconductor chip with the entire back surface covered with the adhesive film. Such a semiconductor chip is obtained by forming a division groove in the front surface of a semiconductor wafer to be divided into plural chips, grinding a back surface of the wafer until the division groove appears to divide the wafer into plural chips, adhering the adhesive film and a dicing tape on the entire back surface of the wafer, and stretching the dicing tape to cut the adhesive film along the division groove.

摘要翻译： 在其表面形成有电子电路的芯片的背面上，粘附至少​​与芯片的背面对应的形状和尺寸的粘合剂膜，以获得整个背面覆盖的半导体芯片 与粘合膜。 这样的半导体芯片通过在半导体晶片的前表面形成分割槽而形成分割槽，从而分割成多个芯片，研磨晶片的背面，直到划分凹槽出现将晶片分成多个芯片， 以及在晶片的整个后表面上的切割胶带，并且拉伸切割带以沿着分割槽切割粘合剂膜。

公开(公告)号：US20070004179A1

公开(公告)日：2007-01-04

申请号：US11472285

申请日：2006-06-22

申请人： Masaru Nakamura ,  Yusuke Nagai

发明人： Masaru Nakamura ,  Yusuke Nagai

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  B23K26/40 ,  B23K2103/50 ,  B28D5/0011

摘要： A method of dividing a wafer having a plurality of devices, which are formed in a plurality of areas sectioned by streets formed in a lattice pattern on the front surface and test metal patterns which are formed on the streets, comprising: a metal pattern breaking step for forming a break line in the test metal patterns by applying a pulse laser beam having permeability to the wafer to the rear surface of the wafer with its focal point set to a position near the test metal patterns; a deteriorated layer forming step for forming a deteriorated layer along the streets above the break lines in the inside of the wafer by applying a pulse laser beam having permeability to the wafer to the rear surface of the wafer with its focal point set to a position above the break lines in the inside of the wafer; and a dividing step for dividing the wafer into individual chips along the deteriorated layers of the wafer by exerting external force to the wafer having the deteriorated layers formed therein.

摘要翻译： 一种分割具有多个装置的晶片的方法，所述晶片形成在由正面上的格子图案形成的街道划分的多个区域中，并且测试形成在街道上的金属图案，包括：金属图案断裂步骤 用于通过将其焦点设置在靠近测试金属图案的位置向晶片的后表面施加具有渗透性的脉冲激光束，从而在测试金属图案中形成断裂线; 劣化层形成步骤，用于通过将具有渗透性的脉冲激光束施加到晶片的后表面，使其焦点设置在晶片的上方，沿着晶片内部的断裂线上方的街道形成劣化层 晶片内部的断裂线; 以及分割步骤，通过向其中形成有劣化层的晶片施加外力，将晶片分割成沿晶片的劣化层的各个芯片。

公开(公告)号：US07087857B2

公开(公告)日：2006-08-08

申请号：US10914152

申请日：2004-08-10

申请人： Masaru Nakamura ,  Toshiyuki Yoshikawa ,  Satoshi Genda

发明人： Masaru Nakamura ,  Toshiyuki Yoshikawa ,  Satoshi Genda

IPC分类号： B23K26/38 ,  H01L21/301

CPC分类号： B28D5/022 ,  B23K26/364 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50

摘要： A method of dividing a plate-like workpiece having a layer that is made of a different material from that of a substrate and is formed on the front surface of the substrate along predetermined dividing lines, comprising a laser beam application step for applying a laser beam to each dividing line formed on the plate-like workpiece except for a non-processed area in at least one end portion thereof to form grooves deeper than the layer; and a cutting step for cutting the plate-like workpiece along each dividing line by positioning a cutting blade on the side of the non-processed area in the dividing line where the grooves have been formed in the laser beam application step and moving the plate-like workpiece relative to the cutting blade while rotating the cutting blade.

摘要翻译： 一种分割具有由不同材料制成的层的板状工件的方法，其特征在于，沿着预定分割线形成在所述基板的前表面上，并且沿着预定分割线形成具有不同材料的层的板状工件，所述方法包括：激光束施加步骤， 到除了在其至少一个端部中的未处理区域之外的形成在板状工件上的每个分割线以形成比该层更深的凹槽; 以及切割步骤，用于通过在激光束施加步骤中在形成有槽的分割线中的未处理区域的侧面上定位切割刀片来沿着分割线切割板状工件， 同时旋转切割刀片时相对于切割刀片的工件。

公开(公告)号：US20060077249A1

公开(公告)日：2006-04-13

申请号：US10937284

申请日：2004-09-10

申请人： Kohji Oshikiri ,  Masaru Nakamura ,  Toshiaki Watanabe ,  Haruo Shida

发明人： Kohji Oshikiri ,  Masaru Nakamura ,  Toshiaki Watanabe ,  Haruo Shida

IPC分类号： G03G15/01 ,  B41J2/385

CPC分类号： G06K15/00 ,  H04L12/18 ,  H04N1/0096 ,  H04N1/32502 ,  H04N1/32512 ,  H04N1/32518 ,  H04N1/32529 ,  H04N1/32534 ,  H04N2201/0094

摘要： In an image forming apparatus in which an input module, an output module, a process module, and a memory have a plurality of ports and are connected by a packet switch having independent paths for data transmission, a path controlling part determines a process path based on data information from the input module and each data transmission ability required to paths within the image forming apparatus, and conducts a selection control to select a data transmission path in response to data transmission delay time for each process path and a data type of data to be transmitted.

摘要翻译： 在其中输入模块，输出模块，处理模块和存储器具有多个端口并且通过具有用于数据传输的独立路径的分组交换机连接的图像形成装置中，路径控制部件基于 对来自输入模块的数据信息和图像形成装置中的路径所需的每个数据传输能力进行选择控制，并且响应于每个处理路径的数据传输延迟时间和数据类型的数据进行选择控制以选择数据传输路径 被传送。