公开(公告)号：US12249605B2

公开(公告)日：2025-03-11

申请号：US17673754

申请日：2022-02-16

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Provided are an inverter including a first source and drain, an interlayer insulating film on the first source, a second source on the interlayer insulating film, a second drain on the first drain, a first channel between the first source and drain, a second channel over the first channel between the second source and drain, a gate insulating film covering outer surfaces of the first and second channel, a part of a surface of the first source in the direction to the first drain, a part of a surface of the second source in the direction to the second drain, a part of a surface of the first drain in the direction to the first source, and a part of a surface of the second drain in the direction to the second source, and a gate electrode between the first source and drain and between the second source and drain.

公开(公告)号：US12154950B2

公开(公告)日：2024-11-26

申请号：US17636342

申请日：2020-11-19

Applicant: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Ji Won Chang ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: Provided is a transistor including: a constant current formation layer; a channel layer provided on the constant current formation layer; a pair of source/drain regions spaced apart from each other, with the channel layer therebetween on the constant current formation layer; a gate electrode provided on the channel layer; and a gate ferroelectric film provided between the gate electrode and the channel layer.

公开(公告)号：US12068381B2

公开(公告)日：2024-08-20

申请号：US17636026

申请日：2020-11-19

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Ji Won Chang ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H03K19/0948

CPC classification number: H01L29/41791 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851 ,  H03K19/0948

Abstract: A transistor includes a substrate; a pair of constant current forming regions provided in the substrate; a pair of source/drain regions respectively provided on the pair of constant current forming regions in the substrate; and a gate structure provided between the pair of source/drain regions, wherein any one of the constant current forming regions immediately adjacent to any one of the pair of source/drain regions serving as a drain forms a constant current between the any one of the pair of source/drain region serving as the drain and the any one of the constant current forming regions.

公开(公告)号：US20220407520A1

公开(公告)日：2022-12-22

申请号：US17673772

申请日：2022-02-16

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim ,  Jae Hyeon Jun

IPC: H03K19/08

Abstract: A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

公开(公告)号：US20220285497A1

公开(公告)日：2022-09-08

申请号：US17636342

申请日：2020-11-19

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Ji Won Chang ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: Provided is a transistor including: a constant current formation layer; a channel layer provided on the constant current formation layer; a pair of source/drain regions spaced apart from each other, with the channel layer therebetween on the constant current formation layer; a gate electrode provided on the channel layer; and a gate ferroelectric film provided between the gate electrode and the channel layer.

公开(公告)号：US20220285484A1

公开(公告)日：2022-09-08

申请号：US17636328

申请日：2020-11-19

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Ji Won Chang ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L29/06 ,  H01L21/265 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: A transistor includes: a substrate; a constant current formation layer provided on the substrate; a pair of source/drain patterns provided on the constant current formation layer; a gate electrode provided between the pair of source/drain patterns; a channel pattern extending in a direction between the pair of source/drain patterns; and a gate insulating layer surrounding the channel pattern, wherein the channel pattern penetrates the gate insulating layer and the gate electrode and is electrically connected to the source pattern and the drain pattern, the gate insulating layer separates the channel pattern and the gate electrode from each other, the constant current formation layer generates a constant current between the drain pattern and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.