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公开(公告)号：US20240334836A1
公开(公告)日：2024-10-03
申请号：US18142036
申请日：2023-05-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ching-Hua Hsu , Che-Wei Chang , Chen-Yi Weng
CPC classification number: H10N50/01 , G11C11/161 , H10B61/00 , H10N50/10 , H10N50/80
Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate comprising a magnetic random access memory (MRAM) region and a logic region, forming a first magnetic tunneling junction (MTJ) on the MRAM region, forming a first inter-metal dielectric (IMD) layer around the first MTJ, and then forming a first metal interconnection extending from the MRAM region to the logic region on the first MTJ. Preferably, the first metal interconnection on the MRAM region and the first metal interconnection on the logic region have different heights.
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公开(公告)号：US20240306514A1
公开(公告)日：2024-09-12
申请号：US18126486
申请日：2023-03-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Che-Wei Chang , Ching-Hua Hsu , Chen-Yi Weng , Po-Kai Hsu
IPC: H10N50/10 , H01L23/522 , H01L23/528 , H10B61/00 , H10N50/80
CPC classification number: H10N50/10 , H01L23/5226 , H01L23/5283 , H10B61/00 , H10N50/80
Abstract: A magnetic random access memory structure includes a first dielectric layer; a bottom electrode layer disposed on the first dielectric layer; a spin orbit coupling layer disposed on the bottom electrode layer; a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer; a top electrode layer disposed on the MTJ element; a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer; and a spacer layer surrounding the protective layer.
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公开(公告)号：US12029139B2
公开(公告)日：2024-07-02
申请号：US18202275
申请日：2023-05-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US20240027549A1
公开(公告)日：2024-01-25
申请号：US18376451
申请日：2023-10-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
CPC classification number: G01R33/093 , G01R33/098 , G11C11/02 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US11821964B2
公开(公告)日：2023-11-21
申请号：US16927918
申请日：2020-07-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
CPC classification number: G01R33/093 , G01R33/098 , G11C11/02 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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Patent Agency Ranking
公开(公告)号：US11706996B2
公开(公告)日：2023-07-18
申请号：US17463541
申请日：2021-08-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US20180076327A1
公开(公告)日：2018-03-15
申请号：US15700193
申请日：2017-09-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Che-Wei Chang , Chun-Hsiung Wang , Chih-Wei Chen
CPC classification number: H01L29/7851 , H01L29/0653 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/785
Abstract: A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a second edge extending along the first direction; a first doped region adjacent to one side of the gate structure, in which the first doped region includes a third edge and a fourth edge extending along the first direction; a second doped region adjacent to another side of the gate structure, in which the second doped region comprises a fifth edge and a sixth edge extending along the first direction; a first fin-shaped structure extending from the second edge of the gate structure toward the third edge of the first doped region; and a second fin-shaped structure extending from the first edge of the gate structure toward the sixth edge of the second doped region.
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公开(公告)号：US20240298547A1
公开(公告)日：2024-09-05
申请号：US18122165
申请日：2023-03-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Che-Wei Chang , Ching-Hua Hsu , Chen-Yi Weng , Po-Kai Hsu
IPC: H10N50/10 , H01L23/522 , H01L23/528 , H10B61/00 , H10N50/80
CPC classification number: H10N50/10 , H01L23/5226 , H01L23/5283 , H10B61/00 , H10N50/80
Abstract: A magnetic random access memory structure includes a first dielectric layer, a bottom electrode layer disposed on the first dielectric layer; a spin orbit coupling layer disposed on the bottom electrode layer; a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer; a top electrode layer disposed on the MTJ element; a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer; a mask layer surrounding the protective layer, and a spacer layer surrounding the mask layer and the protective layer.
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公开(公告)号：US20240027550A1
公开(公告)日：2024-01-25
申请号：US18376843
申请日：2023-10-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
CPC classification number: G01R33/093 , G01R33/098 , G11C11/02 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US11864468B2
公开(公告)日：2024-01-02
申请号：US17348776
申请日：2021-06-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Si-Han Tsai , Dong-Ming Wu , Chen-Yi Weng , Ching-Hua Hsu , Ju-Chun Fan , Yi-Yu Lin , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang
CPC classification number: H10N50/10 , G11C11/161 , H01F10/3254 , H10B61/00 , H10N50/80 , H10N50/85
Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
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