公开(公告)号：US20180076327A1

公开(公告)日：2018-03-15

申请号：US15700193

申请日：2017-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Wei Chang ,  Chun-Hsiung Wang ,  Chih-Wei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/0653 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/785

Abstract: A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a second edge extending along the first direction; a first doped region adjacent to one side of the gate structure, in which the first doped region includes a third edge and a fourth edge extending along the first direction; a second doped region adjacent to another side of the gate structure, in which the second doped region comprises a fifth edge and a sixth edge extending along the first direction; a first fin-shaped structure extending from the second edge of the gate structure toward the third edge of the first doped region; and a second fin-shaped structure extending from the first edge of the gate structure toward the sixth edge of the second doped region.

公开(公告)号：US20150079780A1

公开(公告)日：2015-03-19

申请号：US14026634

申请日：2013-09-13

Applicant: United Microelectronics Corp.

Inventor： Yl-Liang Liu ,  Wu-Sian Sie ,  Po-Cheng Huang ,  Chih-Hsien Chen ,  I-Lun Hung ,  Yen-Ming Chen ,  Yu-Ting Li ,  Chang-Hung Kung ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/78

Abstract: A method of forming a semiconductor device is disclosed. A gate structure is formed on a substrate. The gate structure includes a dummy gate and a spacer at a sidewall of the dummy gate. A dielectric layer is formed on the substrate outside of the gate structure. A metal hard mask layer is formed to cover tops of the dielectric layer and the spacer and to expose a surface of the gate structure. The dummy gate is removed to form a gate trench. A low-resistivity metal layer is formed on the metal hard mask layer filling in the gate trench. The low-resistivity metal layer outside of the gate trench is removed. The metal hard mask layer is removed.

Abstract translation: 公开了一种形成半导体器件的方法。 在基板上形成栅极结构。 栅极结构包括在虚拟栅极的侧壁处的伪栅极和间隔物。 在栅极结构外部的基板上形成电介质层。 形成金属硬掩模层以覆盖电介质层和间隔物的顶部并露出栅极结构的表面。 去除伪栅极以形成栅极沟槽。 在填充在栅极沟槽中的金属硬掩模层上形成低电阻率金属层。 除去栅极沟槽外的低电阻率金属层。 去除金属硬掩模层。

公开(公告)号：US09147612B2

公开(公告)日：2015-09-29

申请号：US14088445

申请日：2013-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  I-Ming Tseng ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Po-Chao Tsao ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/338 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/3086 ,  H01L29/6681

Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

Abstract translation: 本发明提供一种用于形成半导体结构的制造方法，其中首先设置基板，在基板上设置硬掩模，然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模，然后进行图案转印处理，将翅片硬掩模和翅片硬掩模的图案转移到基板中，以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧，并进行翅片切割处理，以去除每个假翅片。

公开(公告)号：US20150214114A1

公开(公告)日：2015-07-30

申请号：US14166091

申请日：2014-01-28

Applicant: United Microelectronics Corp.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chun-Hsiung Wang ,  Kun-Ju Li ,  Chia-Lin Hsu ,  Chih-Chien Liu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/321

CPC classification number: H01L21/823437 ,  H01L21/31051 ,  H01L21/31055 ,  H01L29/66545

Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches.

Abstract translation: 公开了一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供具有形成在其上的多个虚拟栅极结构的基板和覆盖该虚拟栅极结构的第一介电层，所述伪栅极结构包括形成在所述伪栅极上的多个伪栅极和多个绝缘层，其中至少两个 的虚拟门结构具有不同的高度。 执行第一平面化处理以暴露具有最高高度的虚拟栅极结构中的至少一个。 执行第一蚀刻工艺以暴露绝缘层。 进行具有非选择性浆料的化学机械抛光（CMP）工艺以使虚拟栅极结构平坦化。 平面化的虚拟栅极结构被去除以形成多个栅极沟槽。

公开(公告)号：US09837541B1

公开(公告)日：2017-12-05

申请号：US15344602

申请日：2016-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Wei Chang ,  Chun-Hsiung Wang ,  Chih-Wei Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0653 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816

Abstract: A semiconductor device includes: a gate structure on a substrate; a first doped region adjacent to one side of the gate structure; a second doped region adjacent to another side of the gate structure; and fin-shaped structures on the substrate. Preferably, a number of the fin-shaped structures covered by the gate structure is different from a number of the fin-shaped structures overlapping the first doped region or the second doped region.

公开(公告)号：US20150162419A1

公开(公告)日：2015-06-11

申请号：US14102515

申请日：2013-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ting Li ,  Po-Cheng Huang ,  Wu-Sian Sie ,  Chun-Hsiung Wang ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Rai-Min Huang

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/02112 ,  H01L21/02318 ,  H01L21/32055 ,  H01L21/3212 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少包括翅片结构的基板，并且形成材料层以覆盖翅片结构。 然后，在材料层上进行第一平面化处理以形成第一材料层，并且在第一材料层上形成氧化物层。 随后，完全除去氧化物层以露出第一材料层，并且在完全除去氧化物层之后，在第一材料层上原位形成第二材料层。

公开(公告)号：US20140094017A1

公开(公告)日：2014-04-03

申请号：US13633104

申请日：2012-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wu-Sian Sie ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yu-Ting Li ,  Wei-Che Tsao ,  Yen-Ming Chen ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76229

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上依次形成硬掩模层和图案化光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。

公开(公告)号：US10396204B2

公开(公告)日：2019-08-27

申请号：US15700193

申请日：2017-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Wei Chang ,  Chun-Hsiung Wang ,  Chih-Wei Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a second edge extending along the first direction; a first doped region adjacent to one side of the gate structure, in which the first doped region includes a third edge and a fourth edge extending along the first direction; a second doped region adjacent to another side of the gate structure, in which the second doped region comprises a fifth edge and a sixth edge extending along the first direction; a first fin-shaped structure extending from the second edge of the gate structure toward the third edge of the first doped region; and a second fin-shaped structure extending from the first edge of the gate structure toward the sixth edge of the second doped region.

公开(公告)号：US20150147874A1

公开(公告)日：2015-05-28

申请号：US14088445

申请日：2013-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  I-Ming Tseng ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Po-Chao Tsao ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/8234 ,  H01L21/265

CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/3086 ,  H01L29/6681

Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

Abstract translation: 本发明提供一种用于形成半导体结构的制造方法，其中首先设置基板，在基板上设置硬掩模，然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模，然后进行图案转印处理，将翅片硬掩模和翅片硬掩模的图案转移到基板中，以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧，并进行翅片切割处理，以去除每个假翅片。

公开(公告)号：US09012300B2

公开(公告)日：2015-04-21

申请号：US13633104

申请日：2012-10-01

Applicant: United Microelectronics Corp.

Inventor： Wu-Sian Sie ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yu-Ting Li ,  Wei-Che Tsao ,  Yen-Ming Chen ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76229

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上顺序地形成硬掩模层和图案化的光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。