公开(公告)号：US11825648B2

公开(公告)日：2023-11-21

申请号：US17323863

申请日：2021-05-18

Applicant: United Microelectronics Corp.

Inventor： Kuo-Hsing Lee ,  Chi-Horn Pai ,  Chang Chien Wong ,  Sheng-Yuan Hsueh ,  Ching Hsiang Tseng ,  Shih-Chieh Hsu

IPC: H10B20/20

CPC classification number: H10B20/20

Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

公开(公告)号：US20230317715A1

公开(公告)日：2023-10-05

申请号：US17732570

申请日：2022-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Chun-Hsien Lin ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/94 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L29/7851 ,  H01L29/66181 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/94

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

公开(公告)号：US20220302118A1

公开(公告)日：2022-09-22

申请号：US17230975

申请日：2021-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Kun-Hsien Lee ,  Sheng-Yuan Hsueh ,  Chang-Chien Wong ,  Ching-Hsiang Tseng ,  Tsung-Hsun Wu ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H01L27/108

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

公开(公告)号：US20240015958A1

公开(公告)日：2024-01-11

申请号：US18470447

申请日：2023-09-20

Applicant: United Microelectronics Corp.

Inventor： Kuo-Hsing Lee ,  Chi-Horn Pai ,  Chang Chien Wong ,  Sheng-Yuan Hsueh ,  Ching Hsiang Tseng ,  Shih-Chieh Hsu

IPC: H10B20/25

CPC classification number: H10B20/25

Abstract: A one-time programmable memory structure comprises: A transistor includes a gate. A capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is disposed on the first electrode. A top surface of the first electrode and a top surface of the gate are located on a same plane perpendicular to a direction of the first electrode toward the second electrode. An interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode. A resistor comprises a conductive layer. Top and bottom surfaces of the conductive layer are respectively located on a same plane, perpendicular to the direction of the first electrode toward the second electrode, with the top and bottom surfaces of the gate.

公开(公告)号：US20230422491A1

公开(公告)日：2023-12-28

申请号：US17869752

申请日：2022-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Chi-Horn Pai ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

公开(公告)号：US20230380148A1

公开(公告)日：2023-11-23

申请号：US17844076

申请日：2022-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Chih-Kai Kang ,  Ting-Hsiang Huang ,  Chien-Liang Wu ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, forming a first doped region adjacent to the STI, removing part of the STI, and then forming a first gate structure on the substrate and the STI. Preferably, the first gate structure includes a high-k dielectric layer on the substrate and a gate electrode on the high-k dielectric layer, in which the high-k dielectric layer comprises a first L-shape.

公开(公告)号：US11450670B1

公开(公告)日：2022-09-20

申请号：US17230975

申请日：2021-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Kun-Hsien Lee ,  Sheng-Yuan Hsueh ,  Chang-Chien Wong ,  Ching-Hsiang Tseng ,  Tsung-Hsun Wu ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H01L27/108

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

公开(公告)号：US12261169B2

公开(公告)日：2025-03-25

申请号：US17732570

申请日：2022-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Chun-Hsien Lin ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

公开(公告)号：US20230378166A1

公开(公告)日：2023-11-23

申请号：US17844088

申请日：2022-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/7851 ,  H01L29/66795

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a resistor region, forming a first gate structure on the resistor region, forming a first interlayer dielectric (ILD) layer around the first gate structure, transforming the first gate structure into a first metal gate having a gate electrode on the substrate and a hard mask on the gate electrode, and then forming a resistor on the first metal gate.

公开(公告)号：US20220336479A1

公开(公告)日：2022-10-20

申请号：US17323863

申请日：2021-05-18

Applicant: United Microelectronics Corp.

Inventor： Kuo-Hsing Lee ,  Chi-Horn Pai ,  Chang Chien Wong ,  Sheng-Yuan Hsueh ,  Ching Hsiang Tseng ,  Shih-Chieh Hsu

IPC: H01L27/112

Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.