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公开(公告)号:US20220328503A1
公开(公告)日:2022-10-13
申请号:US17314061
申请日:2021-05-07
发明人: Kuo-Hsing Lee , Chang-Chien Wong , Sheng-Yuan Hsueh , Ching-Hsiang Tseng , Chi-Horn Pai , Shih-Chieh Hsu
IPC分类号: H01L27/112
摘要: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.
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公开(公告)号:US09385206B2
公开(公告)日:2016-07-05
申请号:US14919738
申请日:2015-10-22
发明人: Chia-Fu Hsu , Chun-Mao Chiou , Shih-Chieh Hsu , Jian-Cun Ke , Chun-Lung Chen , Lung-En Kuo
CPC分类号: H01L29/495 , H01L21/28088 , H01L21/31116 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/78
摘要: A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.
摘要翻译: 公开了一种半导体器件。 半导体器件包括衬底,衬底上的栅极结构和与栅极结构相邻的间隔物,其中间隔物的底部包括锥形轮廓,并且锥形轮廓包括凸曲线。
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公开(公告)号:US20150357430A1
公开(公告)日:2015-12-10
申请号:US14324092
申请日:2014-07-04
发明人: Chia-Fu Hsu , Chun-Mao Chiou , Shih-Chieh Hsu , Lung-En Kuo , You-Di Jhang , Jian-Cun Ke
CPC分类号: H01L29/6656 , H01L29/401 , H01L29/4966 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.
摘要翻译: 公开了半导体器件的制造方法。 该方法包括以下步骤:提供衬底; 在衬底上形成界面层; 在界面层上形成堆叠结构; 图案化堆叠结构以在界面层上形成栅极结构; 在界面层和栅极结构上形成衬垫; 以及去除衬套的一部分和用于形成间隔物的界面层的一部分。
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公开(公告)号:US20240015958A1
公开(公告)日:2024-01-11
申请号:US18470447
申请日:2023-09-20
发明人: Kuo-Hsing Lee , Chi-Horn Pai , Chang Chien Wong , Sheng-Yuan Hsueh , Ching Hsiang Tseng , Shih-Chieh Hsu
IPC分类号: H10B20/25
CPC分类号: H10B20/25
摘要: A one-time programmable memory structure comprises: A transistor includes a gate. A capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is disposed on the first electrode. A top surface of the first electrode and a top surface of the gate are located on a same plane perpendicular to a direction of the first electrode toward the second electrode. An interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode. A resistor comprises a conductive layer. Top and bottom surfaces of the conductive layer are respectively located on a same plane, perpendicular to the direction of the first electrode toward the second electrode, with the top and bottom surfaces of the gate.
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公开(公告)号:US11450670B1
公开(公告)日:2022-09-20
申请号:US17230975
申请日:2021-04-14
发明人: Kuo-Hsing Lee , Kun-Hsien Lee , Sheng-Yuan Hsueh , Chang-Chien Wong , Ching-Hsiang Tseng , Tsung-Hsun Wu , Chi-Horn Pai , Shih-Chieh Hsu
IPC分类号: H01L27/108
摘要: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.
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公开(公告)号:US11825648B2
公开(公告)日:2023-11-21
申请号:US17323863
申请日:2021-05-18
发明人: Kuo-Hsing Lee , Chi-Horn Pai , Chang Chien Wong , Sheng-Yuan Hsueh , Ching Hsiang Tseng , Shih-Chieh Hsu
IPC分类号: H10B20/20
CPC分类号: H10B20/20
摘要: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.
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公开(公告)号:US20220302118A1
公开(公告)日:2022-09-22
申请号:US17230975
申请日:2021-04-14
发明人: Kuo-Hsing Lee , Kun-Hsien Lee , Sheng-Yuan Hsueh , Chang-Chien Wong , Ching-Hsiang Tseng , Tsung-Hsun Wu , Chi-Horn Pai , Shih-Chieh Hsu
IPC分类号: H01L27/108
摘要: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.
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公开(公告)号:US09196699B1
公开(公告)日:2015-11-24
申请号:US14328720
申请日:2014-07-11
发明人: Chia-Fu Hsu , Chun-Mao Chiou , Shih-Chieh Hsu , Jian-Cun Ke , Chun-Lung Chen , Lung-En Kuo
IPC分类号: H01L21/336 , H01L29/51 , H01L21/28 , H01L29/66
CPC分类号: H01L29/495 , H01L21/28088 , H01L21/31116 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/78
摘要: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; depositing a liner on the gate structure and the substrate; and performing an etching process by injecting a gas comprising CH3F, O2, and He for forming a spacer adjacent to the gate structure.
摘要翻译: 公开了半导体器件的制造方法。 该方法包括以下步骤:提供衬底; 在基板上形成栅极结构; 在栅极结构和衬底上沉积衬垫; 并且通过注入包含CH 3 F,O 2和He的气体来进行蚀刻处理,以形成与栅极结构相邻的间隔物。
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公开(公告)号:US20220336479A1
公开(公告)日:2022-10-20
申请号:US17323863
申请日:2021-05-18
发明人: Kuo-Hsing Lee , Chi-Horn Pai , Chang Chien Wong , Sheng-Yuan Hsueh , Ching Hsiang Tseng , Shih-Chieh Hsu
IPC分类号: H01L27/112
摘要: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.
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公开(公告)号:US20160043195A1
公开(公告)日:2016-02-11
申请号:US14919738
申请日:2015-10-22
发明人: Chia-Fu Hsu , Chun-Mao Chiou , Shih-Chieh Hsu , Jian-Cun Ke , Chun-Lung Chen , Lung-En Kuo
CPC分类号: H01L29/495 , H01L21/28088 , H01L21/31116 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/78
摘要: A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.
摘要翻译: 公开了一种半导体器件。 半导体器件包括衬底,衬底上的栅极结构和与栅极结构相邻的间隔物,其中间隔物的底部包括锥形轮廓,并且锥形轮廓包括凸曲线。
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