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公开(公告)号:US20220302118A1
公开(公告)日:2022-09-22
申请号:US17230975
申请日:2021-04-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Kun-Hsien Lee , Sheng-Yuan Hsueh , Chang-Chien Wong , Ching-Hsiang Tseng , Tsung-Hsun Wu , Chi-Horn Pai , Shih-Chieh Hsu
IPC: H01L27/108
Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.
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公开(公告)号:US20220392905A1
公开(公告)日:2022-12-08
申请号:US17363015
申请日:2021-06-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Chun-Hsien Lin , Chih-Wei Yang , Chang-Chien Wong , Te-Wei Yeh , Sheng-Yuan Hsueh
IPC: H01L27/112
Abstract: A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.
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公开(公告)号:US11450670B1
公开(公告)日:2022-09-20
申请号:US17230975
申请日:2021-04-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Kun-Hsien Lee , Sheng-Yuan Hsueh , Chang-Chien Wong , Ching-Hsiang Tseng , Tsung-Hsun Wu , Chi-Horn Pai , Shih-Chieh Hsu
IPC: H01L27/108
Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.
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公开(公告)号:US20220328503A1
公开(公告)日:2022-10-13
申请号:US17314061
申请日:2021-05-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Chang-Chien Wong , Sheng-Yuan Hsueh , Ching-Hsiang Tseng , Chi-Horn Pai , Shih-Chieh Hsu
IPC: H01L27/112
Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.
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公开(公告)号:US11322215B1
公开(公告)日:2022-05-03
申请号:US17326375
申请日:2021-05-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Pin Tsao , Tsung-Hsun Wu , Liang-Wei Chiu , Kuo-Hsing Lee , Sheng-Yuan Hsueh , Kun-Hsien Lee , Chang-Chien Wong
Abstract: A one-time programmable (OTP) memory device includes a first memory cell, which further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on another side of the first source line, a first diffusion region extending along a second direction adjacent to two sides of the first word line and the second word line, and a first metal interconnection connecting the first word line and the second word line.
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公开(公告)号:US20230247827A1
公开(公告)日:2023-08-03
申请号:US18134041
申请日:2023-04-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Chang-Chien Wong , Sheng-Yuan Hsueh , Ching-Hsiang Tseng , Chi-Horn Pai , Shih-Chieh Hsu
IPC: H10B20/25
CPC classification number: H10B20/25
Abstract: A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.
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公开(公告)号:US11665891B2
公开(公告)日:2023-05-30
申请号:US17314061
申请日:2021-05-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Chang-Chien Wong , Sheng-Yuan Hsueh , Ching-Hsiang Tseng , Chi-Horn Pai , Shih-Chieh Hsu
IPC: H10B20/20
CPC classification number: H10B20/20
Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.
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