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公开(公告)号:US20230299158A1
公开(公告)日:2023-09-21
申请号:US17719351
申请日:2022-04-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuan-Yu Lu , Hou-Jen Chiu , Mei-Ling Chao , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L29/417 , H01L23/522 , H01L27/02
CPC classification number: H01L29/41775 , H01L23/5226 , H01L27/0266 , H01L29/7835
Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a gate structure, a source doped region, a drain doped region, source silicide patterns, and drain silicide patterns. The gate structure is disposed on the semiconductor substrate. The source doped region and the drain doped region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction, respectively. The source silicide patterns are disposed on the source doped region. The source silicide patterns are arranged in a second direction and separated from one another. The drain silicide patterns are disposed on the drain doped region. The drain silicide patterns are arranged in the second direction and separated from one another. The source silicide patterns and the drain silicide patterns are arranged misaligned with one another in the first direction.
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公开(公告)号:US10546849B2
公开(公告)日:2020-01-28
申请号:US15247134
申请日:2016-08-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chung-Yu Huang , Hou-Jen Chiu , Tien-Hao Tang
Abstract: A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region.
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公开(公告)号:US10062751B2
公开(公告)日:2018-08-28
申请号:US15402204
申请日:2017-01-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hou-Jen Chiu , Ya-Ting Lin , Mei-Ling Chao , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L27/088 , H01L29/06 , H01L29/78
CPC classification number: H01L29/0638 , H01L29/0653 , H01L29/785
Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.
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公开(公告)号:US20180114787A1
公开(公告)日:2018-04-26
申请号:US15365602
申请日:2016-11-30
Applicant: United Microelectronics Corp.
Inventor: Heng-Yu Lin , Kuei-Chih Fan , Hou-Jen Chiu , Mei-Ling Chao , Tien-Hao Tang
CPC classification number: H01L27/0274 , H01L29/1095 , H01L29/408 , H01L29/7816 , H01L29/7835
Abstract: An ESD protection device on a substrate includes a base doped region of a first conductivity type. A first inter doped region of a second conductivity type is in the base doped region. A drain region of the second conductivity type in the first inter doped region is connected to a first electrode terminal. An inserted doped region of the first conductivity type is in the drain region. A second inter doped region of the second conductivity type is in the base doped region. A source region of the second conductivity type is in the second inter doped region. A substrate-surface doped region of the first conductivity type in the substrate is adjacent to or in contact with the source region. A gate structure is between the drain and source regions in the substrate. The substrate-surface doped region and the source region are connected to a second electrode terminal.
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