公开(公告)号：US20180158902A1

公开(公告)日：2018-06-07

申请号：US15402204

申请日：2017-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hou-Jen Chiu ,  Ya-Ting Lin ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L29/0653 ,  H01L29/7851

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

公开(公告)号：US20230299158A1

公开(公告)日：2023-09-21

申请号：US17719351

申请日：2022-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Yu Lu ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/417 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L27/0266 ,  H01L29/7835

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a gate structure, a source doped region, a drain doped region, source silicide patterns, and drain silicide patterns. The gate structure is disposed on the semiconductor substrate. The source doped region and the drain doped region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction, respectively. The source silicide patterns are disposed on the source doped region. The source silicide patterns are arranged in a second direction and separated from one another. The drain silicide patterns are disposed on the drain doped region. The drain silicide patterns are arranged in the second direction and separated from one another. The source silicide patterns and the drain silicide patterns are arranged misaligned with one another in the first direction.

公开(公告)号：US10062751B2

公开(公告)日：2018-08-28

申请号：US15402204

申请日：2017-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hou-Jen Chiu ,  Ya-Ting Lin ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L29/0653 ,  H01L29/785

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

公开(公告)号：US20180114787A1

公开(公告)日：2018-04-26

申请号：US15365602

申请日：2016-11-30

Applicant: United Microelectronics Corp.

Inventor： Heng-Yu Lin ,  Kuei-Chih Fan ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L27/0274 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/7816 ,  H01L29/7835

Abstract: An ESD protection device on a substrate includes a base doped region of a first conductivity type. A first inter doped region of a second conductivity type is in the base doped region. A drain region of the second conductivity type in the first inter doped region is connected to a first electrode terminal. An inserted doped region of the first conductivity type is in the drain region. A second inter doped region of the second conductivity type is in the base doped region. A source region of the second conductivity type is in the second inter doped region. A substrate-surface doped region of the first conductivity type in the substrate is adjacent to or in contact with the source region. A gate structure is between the drain and source regions in the substrate. The substrate-surface doped region and the source region are connected to a second electrode terminal.

公开(公告)号：US09691752B1

公开(公告)日：2017-06-27

申请号：US15096234

申请日：2016-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L27/0277 ,  H01L29/0619 ,  H01L29/7816

Abstract: An ESD protection device and a method of forming the same, the ESD device includes a substrate, a first doped well, a second doped well, a source and drain regions and a guard ring. The first doped well with a first conductive type is disposed in the substrate. The source and drain regions with the second conductive type are disposed in the first doped well. The guard ring with the first conductive type is also disposed in the first doped well and has a first portion extending along a first direction and a second portion extending along a second direction different from the first direction. The second doped well with the second conductive type is also disposed in the first doped well between the drain region and the second portion of the guard ring to in contact with the drain region in the first direction.

公开(公告)号：US08748278B2

公开(公告)日：2014-06-10

申请号：US14069179

申请日：2013-10-31

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device is provided. A fin of a first conductivity type is formed on a substrate of the first conductivity type. A gate is formed on the substrate, wherein the gate covers a portion of the fin. Source and drain regions of a second conductivity type are formed in the fin at respective sides of the gate. A punch-through stopper (PTS) of the first conductivity type is formed in the fin underlying the gate and between the source and drain regions, wherein the PTS has an impurity concentration higher than that of the substrate. A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS.

Abstract translation: 提供一种制造半导体器件的方法。 在第一导电类型的衬底上形成第一导电类型的鳍。 栅极形成在衬底上，其中栅极覆盖鳍片的一部分。 第二导电类型的源极和漏极区域形成在栅极的相应侧的翅片中。 第一导电类型的穿通止动件（PTS）形成在栅极下方的栅极和源极和漏极区域之间，其中PTS的杂质浓度高于衬底的杂质浓度。 将第二导电类型的第一杂质注入到PTS中，以补偿PTS的杂质浓度。

公开(公告)号：US12211833B2

公开(公告)日：2025-01-28

申请号：US17742392

申请日：2022-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

公开(公告)号：US20240194668A1

公开(公告)日：2024-06-13

申请号：US18105256

申请日：2023-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsuan Lin ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/082 ,  H01L29/08

CPC classification number: H01L27/0259 ,  H01L27/082 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/735

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.

公开(公告)号：US10090291B2

公开(公告)日：2018-10-02

申请号：US15138226

申请日：2016-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: A layout structure of an ESD protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped regions, at least a first gate structure formed within the first doped region, and a drain region and a first source region formed at two sides of the first gate structure. The substrate, the first doped region and the third doped regions include a first conductivity type. The second doped regions, the drain region and the first source region include a second conductivity type complementary to the first conductivity type. The first doped region includes a pair of lateral portions and a pair of vertical portions. The pair of second doped regions is formed under the pair of lateral portions, and the pair of third doped regions is formed under the pair of vertical portions.

公开(公告)号：US20250120185A1

公开(公告)日：2025-04-10

申请号：US18981624

申请日：2024-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.