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公开(公告)号：US20240237550A1
公开(公告)日：2024-07-11
申请号：US18611753
申请日：2024-03-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jin-Yan Chiou , Wei-Chuan Tsai , Hsin-Fu Huang , Yen-Tsai Yi , Hsiang-Wen Ke
CPC classification number: H10N50/80 , G11C11/161 , H10N50/01 , H01F10/3254 , H01F41/32 , H10N50/85
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a
MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.-
公开(公告)号：US20220122915A1
公开(公告)日：2022-04-21
申请号：US17073413
申请日：2020-10-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Tsai Yi , Wei-Chuan Tsai , Jin-Yan Chiou , Hsiang-Wen Ke
IPC: H01L23/535 , H01L23/522 , H01L23/532 , H01L21/321 , H01L21/768
Abstract: A semiconductor structure includes a substrate; a first inter-layer dielectric (ILD) layer on the substrate; an etch stop layer on the first ILD layer; a second inter-layer dielectric (ILD) layer on the etch stop layer; and a copper damascene interconnect layer disposed in the first ILD layer. A tungsten via structure is disposed in the second ILD layer and the etch stop layer, and is electrically connected to the copper damascene interconnect layer. The tungsten via structure includes a tungsten layer and a barrier layer surrounding the tungsten layer. An intermetallic layer is disposed between the barrier layer and the copper damascene interconnect layer.
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Patent Agency Ranking
公开(公告)号：US20250089448A1
公开(公告)日：2025-03-13
申请号：US18381646
申请日：2023-10-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Tsai Yi , Wei-Chuan Tsai , Jin-Yan Chiou , Hsiang-Wen Ke
IPC: H10K50/81 , H10K50/11 , H10K50/82 , H10K50/856 , H10K59/131
Abstract: An organic light-emitting diode display device includes a first light-emitting layer, a first anode, a first reflective pattern, and a dielectric material. The first light-emitting layer, the first anode, and the first reflective pattern are located in a first sub-pixel region. The first anode is disposed under the first light-emitting layer in a vertical direction, and the first reflective pattern is disposed under the first anode in the vertical direction. The dielectric material is partly disposed between the first anode and the first reflective pattern, and the first reflective pattern is electrically connected with the first anode.
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公开(公告)号：US20240397832A1
公开(公告)日：2024-11-28
申请号：US18791383
申请日：2024-07-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Tsai Yi , Wei-Chuan Tsai , Jin-Yan Chiou , Hsiang-Wen Ke
Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunneling junction (MTJ) on a substrate, a first top electrode on the MTJ, a second top electrode on and directly contacting the first top electrode, and a spacer adjacent to the MTJ. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.
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公开(公告)号：US20240237549A1
公开(公告)日：2024-07-11
申请号：US18610212
申请日：2024-03-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jin-Yan Chiou , Wei-Chuan Tsai , Hsin-Fu Huang , Yen-Tsai Yi , Hsiang-Wen Ke
CPC classification number: H10N50/80 , G11C11/161 , H10N50/01 , H01F10/3254 , H01F41/32 , H10N50/85
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
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公开(公告)号：US11968906B2
公开(公告)日：2024-04-23
申请号：US16882552
申请日：2020-05-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jin-Yan Chiou , Wei-Chuan Tsai , Hsin-Fu Huang , Yen-Tsai Yi , Hsiang-Wen Ke
CPC classification number: H10N50/80 , G11C11/161 , H10N50/01 , H01F10/3254 , H01F41/32 , H10N50/85
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
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公开(公告)号：US20230387280A1
公开(公告)日：2023-11-30
申请号：US17851048
申请日：2022-06-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Tsai Yi , Wei-Chuan Tsai , Jin-Yan Chiou , Hsiang-Wen Ke
IPC: H01L29/778 , H01L29/20 , H01L29/08 , H01L29/66
CPC classification number: H01L29/7783 , H01L29/2003 , H01L29/0847 , H01L29/66462
Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a titanium nitride (TiN) layer on the p-type semiconductor layer as a nitrogen to titanium (N/Ti) ratio of the TiN layer is greater than 1, forming a passivation layer on the TiN layer and the barrier layer, removing the passivation layer to form an opening, forming a gate electrode in the opening, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer.
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