公开(公告)号：US12279536B2

公开(公告)日：2025-04-15

申请号：US18610212

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  G11C11/16 ,  H10N50/01 ,  H10N50/85 ,  H01F10/32 ,  H01F41/32

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

公开(公告)号：US11450564B2

公开(公告)日：2022-09-20

申请号：US16568266

申请日：2019-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Li-Han Chen ,  Hsiang-Wen Ke

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.

公开(公告)号：US20230125856A1

公开(公告)日：2023-04-27

申请号：US17533146

申请日：2021-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Wen Ke ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Jin-Yan Chiou

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

Abstract: A method for fabricating a semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a barrier layer in the trench, forming a nucleation layer on the barrier layer, performing an anneal process to form a silicide layer, forming a bulk layer on the silicide layer, and forming a magnetic tunneling junction (MTJ) on the bulk layer.

公开(公告)号：US20210343931A1

公开(公告)日：2021-11-04

申请号：US16882552

申请日：2020-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

公开(公告)号：US20250081568A1

公开(公告)日：2025-03-06

申请号：US18950155

申请日：2024-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H01L29/45 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

公开(公告)号：US20230094638A1

公开(公告)日：2023-03-30

申请号：US17510394

申请日：2021-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H01L29/45 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

公开(公告)号：US20220384710A1

公开(公告)日：2022-12-01

申请号：US17361331

申请日：2021-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.

公开(公告)号：US20210050253A1

公开(公告)日：2021-02-18

申请号：US16568266

申请日：2019-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Li-Han Chen ,  Hsiang-Wen Ke

IPC: H01L21/768 ,  H01L21/285 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.

公开(公告)号：US12183801B2

公开(公告)日：2024-12-31

申请号：US17510394

申请日：2021-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H01L29/45 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

公开(公告)号：US12089504B2

公开(公告)日：2024-09-10

申请号：US17361331

申请日：2021-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.