公开(公告)号：US12211888B2

公开(公告)日：2025-01-28

申请号：US17160319

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chi-Mao Hsu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Hsin-Fu Huang

IPC: H01C17/08 ,  H01C7/00 ,  H01L49/02

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

公开(公告)号：US20200266199A1

公开(公告)日：2020-08-20

申请号：US16866573

申请日：2020-05-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

公开(公告)号：US09985110B2

公开(公告)日：2018-05-29

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L29/267 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US09653300B2

公开(公告)日：2017-05-16

申请号：US13864218

申请日：2013-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L27/148 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/28088 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

Abstract: A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.

公开(公告)号：US09640482B1

公开(公告)日：2017-05-02

申请号：US15097301

申请日：2016-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Min-Chuan Tsai ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Kuo-Chin Hung ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L29/45 ,  H01L23/522

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266

Abstract: The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.

公开(公告)号：US09130032B2

公开(公告)日：2015-09-08

申请号：US14465579

申请日：2014-08-21

Applicant: United Microelectronics Corp.

Inventor： Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Provided is a semiconductor device including a substrate, a gate structure, a second dielectric layer and a source/drain region. A first dielectric layer is disposed on the substrate, and the first dielectric layer has a trench therein. The gate structure is disposed on the substrate in the trench and includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench, and includes a TiAl3 phase metal layer. A height of the work function metal layer disposed on a sidewall of the trench is lower than a height of a top surface of the first dielectric layer. The metal layer fills the trench. The second dielectric layer is disposed between the gate structure and the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure.

Abstract translation: 提供了一种包括基板，栅极结构，第二介电层和源极/漏极区域的半导体器件。 第一电介质层设置在基板上，并且第一介电层在其中具有沟槽。 栅极结构设置在沟槽中的衬底上，并且包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括TiAl 3相金属层。 布置在沟槽的侧壁上的功函数金属层的高度低于第一电介质层的顶表面的高度。 金属层填充沟槽。 第二电介质层设置在栅极结构和衬底之间。 源极/漏极区域在栅极结构的两侧设置在衬底中。

公开(公告)号：US20140374909A1

公开(公告)日：2014-12-25

申请号：US14480648

申请日：2014-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chin-Fu Lin ,  JING-GANG LI ,  Min-Hsien Chen ,  JIAN-HONG SU

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76846 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.

Abstract translation: 公开了一种用金属层填充沟槽的方法。 提供具有多个支撑销的沉积装置。 设置有基板和介电层。 电介质层具有沟槽。 在将衬底放置在支撑销上以在沟槽中形成金属层之后立即执行第一沉积工艺，其中在第一沉积工艺期间，衬底的温度逐渐增加以达到预定温度。 当基板的温度达到预定温度时，执行第二沉积工艺以用金属层完全填充沟槽。 本发明还提供了具有大于1的反射率的铝层的半导体器件，其中通过使用该方法形成半导体器件。

公开(公告)号：US08735269B1

公开(公告)日：2014-05-27

申请号：US13741402

申请日：2013-01-15

Applicant: United Microelectronics Corp.

Inventor： Chi-Yuan Sun ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chin-Fu Lin

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

Abstract: The method for forming a semiconductor structure includes first providing a substrate. Then, a TiN layer is formed on the substrate at a rate between 0.3 and 0.8 angstrom/second. Finally, a poly-silicon layer is formed directly on the TiN layer. Since the TiN in the barrier layer is formed at a low rate so as to obtain a good quality, the defects in the TiN layer or the defects on the above layer, such as gate dummy layer or gate cap layer, can be avoided.

Abstract translation: 形成半导体结构的方法包括首先提供衬底。 然后，以0.3〜0.8埃的速度在基板上形成TiN层。 最后，直接在TiN层上形成多晶硅层。 由于阻挡层中的TiN以低的速率形成以获得良好的质量，因此可以避免TiN层中的缺陷或上层的缺陷，例如栅极虚设层或栅极盖层。

公开(公告)号：US12237395B2

公开(公告)日：2025-02-25

申请号：US17676216

申请日：2022-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/768 ,  H01L29/20 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US20240237549A1

公开(公告)日：2024-07-11

申请号：US18610212

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  G11C11/16 ,  H01F10/32 ,  H01F41/32 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10N50/01 ,  H01F10/3254 ,  H01F41/32 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.