公开(公告)号：US11238912B1

公开(公告)日：2022-02-01

申请号：US17146424

申请日：2021-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Jen-Yu Wang ,  Yung-Ching Hsieh ,  Po-Chun Yang ,  Jian-Jhong Chen ,  Bo-Chang Li

IPC: G11C11/16 ,  H01L27/22

Abstract: In an MRAM, each unit cell includes two non-volatile storage units, three N-type transistors and three P-type transistors. Each N-type transistor is coupled in parallel with a corresponding P-type transistor for forming a transmission gate which provides bi-directional current, thereby preventing source degeneration.

公开(公告)号：US20210183944A1

公开(公告)日：2021-06-17

申请号：US16746974

申请日：2020-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jian-Jhong Chen ,  Po-Chun Yang ,  Jhen-Siang Wu ,  Yung-Ching Hsieh ,  Bo-Chang Li ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.

公开(公告)号：US20230343379A1

公开(公告)日：2023-10-26

申请号：US17744746

申请日：2022-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Tung Huang ,  Jen-Yu Wang ,  Po-Chun Yang ,  Yi-Ting Wu ,  Yung-Ching Hsieh ,  Jian-Jhong Chen ,  Chia-Wei Lee

IPC: G11C11/16

CPC classification number: G11C11/1673

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

公开(公告)号：US20220384523A1

公开(公告)日：2022-12-01

申请号：US17368848

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Jen-Yu Wang ,  Yung-Ching Hsieh ,  Po-Chun Yang ,  Jian-Jhong Chen ,  Bo-Chang Li

IPC: H01L27/22 ,  H01L43/02

Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

公开(公告)号：US11018185B1

公开(公告)日：2021-05-25

申请号：US16746974

申请日：2020-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jian-Jhong Chen ,  Po-Chun Yang ,  Jhen-Siang Wu ,  Yung-Ching Hsieh ,  Bo-Chang Li ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.

公开(公告)号：US10651235B1

公开(公告)日：2020-05-12

申请号：US16296225

申请日：2019-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jhen-Siang Wu ,  Po-Chun Yang ,  Yung-Ching Hsieh ,  Zong-Sheng Zheng ,  Jian-Jhong Chen ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/08

Abstract: A first MRAM set includes a first transistor and a second transistor. The first transistor includes a first gate structure, a first source/drain doping region and a first common source/drain doping region. The second transistor includes a second gate structure, a second source/drain doping region and the first common source/drain doping region. A second MTJ is disposed on the second transistor. The first common source/drain doping region electrically connects to the second MTJ. A first MTJ is disposed on the first transistor. The sizes of the first MTJ and the second MTJ are different. The second MTJ connects to the first MTJ in series. A bit line electrically connects the first MTJ. A source line electrically connects to the first source/drain doping region and the second source/drain doping region.