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公开(公告)号：US10529667B1
公开(公告)日：2020-01-07
申请号：US16049826
申请日：2018-07-31
Inventor： Zheng-Feng Chen , Sho-Shen Lee , En-Chiuan Liou , Hsiao-Lin Hsu , Yi-Ting Chen , Lu-Wei Kuo
IPC: H01L23/544 , H01L27/108 , H01L21/027 , H01L21/3213 , H01L21/311
Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.
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公开(公告)号：US10276395B2
公开(公告)日：2019-04-30
申请号：US15928078
申请日：2018-03-21
Inventor： Chien-Hao Chen , Feng-Lun Wu , Chung-Ping Hsia , Sho-Shen Lee
IPC: H01L21/30 , H01L21/308 , H01L21/027 , G03F7/09 , H01L23/544 , H01L27/105
Abstract: The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.
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公开(公告)号：US20180286692A1
公开(公告)日：2018-10-04
申请号：US15928078
申请日：2018-03-21
Inventor： Chien-Hao Chen , Feng-Lun Wu , Chung-Ping Hsia , Sho-Shen Lee
IPC: H01L21/308 , H01L21/027 , G03F7/09
CPC classification number: H01L21/3088 , G03F7/091 , H01L21/0276 , H01L21/3085 , H01L21/3086 , H01L23/544 , H01L27/105 , H01L2223/54426
Abstract: The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.
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公开(公告)号：US20160307850A1
公开(公告)日：2016-10-20
申请号：US14687912
申请日：2015-04-15
Applicant: United Microelectronics Corp.
Inventor： Chia-Ching Lin , En-Chiuan Liou , Chia-Hung Wang , Sho-Shen Lee
IPC: H01L23/544 , H01L29/78
CPC classification number: H01L29/785 , G03F7/70633 , G03F7/70683
Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.
Abstract translation: 在本发明中提供了用于确定在衬底上方与两个连续层形成的两个单独产生的图案之间的对准的覆盖标记，其中衬底和覆盖标记都包括具有不同取向的周期性结构的至少两个图案区域，以及 覆盖标记的周期性结构与衬底的周期性结构正交地重叠。
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公开(公告)号：US10763264B2
公开(公告)日：2020-09-01
申请号：US16571202
申请日：2019-09-16
Inventor： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang , Sho-Shen Lee
IPC: H01L27/108 , G11C11/401
Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
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Patent Agency Ranking
公开(公告)号：US10692785B2
公开(公告)日：2020-06-23
申请号：US16057826
申请日：2018-08-08
Inventor： Chien-Hao Chen , Chien-Wei Huang , Chia-Hung Wang , Sho-Shen Lee
Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
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公开(公告)号：US20200111791A1
公开(公告)日：2020-04-09
申请号：US16178521
申请日：2018-11-01
Inventor： Chia-Hung Wang , En-Chiuan Liou , Chien-Hao Chen , Sho-Shen Lee , Yi-Ting Chen , Jhao-Hao Lee
IPC: H01L27/108 , H01L21/033 , H01L21/027 , H01L21/311
Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
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公开(公告)号：US20200013724A1
公开(公告)日：2020-01-09
申请号：US16049826
申请日：2018-07-31
Inventor： Zheng-Feng Chen , Sho-Shen Lee , En-Chiuan Liou , Hsiao-Lin Hsu , Yi-Ting Chen , Lu-Wei Kuo
IPC: H01L23/544 , H01L27/108 , H01L21/027 , H01L21/311 , H01L21/3213
Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.
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公开(公告)号：US20190273083A1
公开(公告)日：2019-09-05
申请号：US15936396
申请日：2018-03-26
Inventor： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang , Sho-Shen Lee
IPC: H01L27/108 , G11C11/401
Abstract: The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
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公开(公告)号：US10177094B1
公开(公告)日：2019-01-08
申请号：US15954591
申请日：2018-04-16
Inventor： Hsiao-Lin Hsu , En-Chiuan Liou , Yi-Ting Chen , Sho-Shen Lee
IPC: H01L23/544 , G01B11/27 , H01L21/66 , H01L21/8234
Abstract: A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.
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