公开(公告)号：US20180061963A1

公开(公告)日：2018-03-01

申请号：US15252200

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US09755057B1

公开(公告)日：2017-09-05

申请号：US15221611

申请日：2016-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Shui-Yen Lu

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.

公开(公告)号：US20140367798A1

公开(公告)日：2014-12-18

申请号：US14470957

申请日：2014-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract translation: 提供一种形成翅片结构的方法。 首先，提供衬底，其中第一区域，包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后，在第一区域和第二区域中形成具有第一深度的多个第一沟槽，其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后，加深第一沟槽以形成具有第二深度的多个第二沟槽，其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。

公开(公告)号：US12274081B2

公开(公告)日：2025-04-08

申请号：US18519099

申请日：2023-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H10D30/47 ,  H01L21/311 ,  H10D30/01 ,  H10D62/85

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US20250107130A1

公开(公告)日：2025-03-27

申请号：US18976256

申请日：2024-12-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a first passivation layer on the insulating layer, a contact structure disposed on the first passivation layer and extending through the first passivation layer to directly contact a portion of the barrier layer, and an insulating layer interposed between the barrier layer and the first passivation layer and comprising an extending portion protruding toward a bottom corner of the contact structure.

公开(公告)号：US12218229B2

公开(公告)日：2025-02-04

申请号：US17396793

申请日：2021-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, a stacked structure on the substrate, an insulating layer on the stacked structure, a passivation layer on the insulating layer, and a contact structure through the passivation layer and the insulating layer and directly contacting the stacked structure. The insulating layer has an extending portion protruding from a sidewall of the passivation layer and adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US20240088279A1

公开(公告)日：2024-03-14

申请号：US18519099

申请日：2023-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7781 ,  H01L21/31116 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US20230102890A1

公开(公告)日：2023-03-30

申请号：US18075427

申请日：2022-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Ming-Hua Chang ,  Shui-Yen Lu

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/06 ,  H01L29/205 ,  H01L29/20

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

公开(公告)号：US20220069102A1

公开(公告)日：2022-03-03

申请号：US17523946

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US11205710B2

公开(公告)日：2021-12-21

申请号：US16357333

申请日：2019-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L29/78

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.