公开(公告)号：US09337084B1

公开(公告)日：2016-05-10

申请号：US14846822

申请日：2015-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Kun-Yuan Liao ,  Chun-Lung Chen ,  Ching-Pin Hsu ,  Shang-Yuan Tsai

IPC: H01L21/768 ,  H01L27/11

CPC classification number: H01L21/76816 ,  H01L21/76801 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

Abstract: The present invention provides a method for manufacturing contact holes of a semiconductor device, including a first dielectric layer is provided, a first region and a second region are defined on the first dielectric layer respectively, at least two cutting hard masks are formed and disposed within the first region and the second region respectively, at least two step-height portions disposed right under the cutting hard masks respectively. Afterwards, at least one first slot opening within the first region is formed, where the first slot opening partially overlaps the cutting hard mask and directly contacts the cutting hard mask, and at least one second contact opening is formed within the second region, where the second contact opening does not contact the cutting hard mask directly, and at least two contact holes are formed, where each contact hole penetrates through each step height portion.

Abstract translation: 本发明提供了一种用于制造半导体器件的接触孔的方法，包括第一介电层，第一介电层和第二区分别形成在第一介电层上，形成至少两个切割硬掩模， 第一区域和第二区域分别设置在切割硬掩模正下方的至少两个台阶部分。 之后，形成在第一区域内的至少一个第一狭槽开口，其中第一狭槽开口部分地与切割硬掩模重叠并且直接接触切割硬掩模，并且在第二区域内形成至少一个第二接触开口， 第二接触开口不直接接触切割硬掩模，并且形成至少两个接触孔，其中每个接触孔穿过每个台阶高度部分。

公开(公告)号：US20210242110A1

公开(公告)日：2021-08-05

申请号：US16835349

申请日：2020-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/768 ,  H01L21/02 ,  H01L23/485 ,  H01L21/762

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

公开(公告)号：US09023708B2

公开(公告)日：2015-05-05

申请号：US13866456

申请日：2013-04-19

Applicant: United Microelectronics Corp.

Inventor： Li-Chiang Chen ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai ,  Ching-Pin Hsu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。