公开(公告)号：US20210143267A1

公开(公告)日：2021-05-13

申请号：US17151683

申请日：2021-01-19

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chuan-Chang Wu ,  Zhen Wu ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/764 ,  H01L29/786

摘要： A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.

公开(公告)号：US20210013325A1

公开(公告)日：2021-01-14

申请号：US16544830

申请日：2019-08-19

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chuan-Chang Wu ,  Zhen Wu ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/764

摘要： A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.

公开(公告)号：US09711646B2

公开(公告)日：2017-07-18

申请号：US14230223

申请日：2014-03-31

申请人： United Microelectronics Corp.

发明人： Yu-Ping Wang ,  Jyh-Shyang Jenq ,  Yu-Hsiang Lin ,  Hsuan-Hsu Chen ,  Chien-Hao Chen ,  Yi-Han Ye

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

公开(公告)号：US09230812B2

公开(公告)日：2016-01-05

申请号：US13899577

申请日：2013-05-22

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chieh-Te Chen ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen ,  Feng-Yi Chang

IPC分类号： H01L21/311 ,  H01L21/28 ,  H01L21/768 ,  H01L21/033

CPC分类号： H01L21/28 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76816

摘要： A method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. A pattern density of the first region is substantially greater than that of the second region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.

摘要翻译： 提供一种形成具有开口的半导体结构的方法。 首先，提供衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 第一区域的图案密度基本上大于第二区域的图案密度。 然后，在基板上形成材料层。 第一硬掩模和第二硬掩模形成在材料层上。 第一区域中的第一硬掩模被去除以形成图案化的第一硬掩模。 去除第三区域中的第二硬掩模以形成图案化的第二硬掩模。 最后，通过使用图案化的第二硬掩模层作为掩模来对材料层进行图案化，以仅在第三区域中形成至少一个开口。

公开(公告)号：US20140346575A1

公开(公告)日：2014-11-27

申请号：US13902975

申请日：2013-05-27

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen

IPC分类号： H01L21/283 ,  H01L21/311 ,  H01L29/417

CPC分类号： H01L29/41775 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with a self-aligned contact and a method of manufacturing the same, wherein the method comprises the step of forming a 1st dielectric layer on gate structures, form a self-aligned contact trench between two gate structures, forming an 2nd dielectric layer on the 1st dielectric layer and in the self-aligned contact trench; patterning the 2nd dielectric layer into a 1st portion on the 1st dielectric layer and a 2nd portion filling in the self-aligned contact trench, using the 2nd dielectric layer as a mask to etch the 1st dielectric layer, and forming a metal layer and a self-aligned contact simultaneously in the 1st dielectric layer and in the self-aligned contact trench.

摘要翻译： 具有自对准接触的半导体器件及其制造方法，其中所述方法包括在栅极结构上形成第一介电层的步骤，在两个栅极结构之间形成自对准接触沟槽，形成第二介电层 在第一电介质层和自对准接触沟槽中; 将第二电介质层图案化为第一介电层上的第一部分，并且使用第二介电层作为掩模来蚀刻第一介电层，并形成金属层和自身的第二部分填充在自对准接触沟槽中 在第一电介质层和自对准接触沟槽中同时进行。

公开(公告)号：US11990346B2

公开(公告)日：2024-05-21

申请号：US17391075

申请日：2021-08-02

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chuan-Chang Wu ,  Zhen Wu ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L29/66

CPC分类号： H01L21/32134 ,  H01L29/66545

摘要： A method for a clean procedure during manufacturing a semiconductor device, includes: providing a patterned sacrificial gate structure including a gate dielectric and a sacrificial layer; wherein the patterned sacrificial gate structure is embedded in a dielectric layer and an upper surface of the sacrificial layer is exposed; performing a first etching process to remove the sacrificial layer; and performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer.

公开(公告)号：US20240016062A1

公开(公告)日：2024-01-11

申请号：US17874327

申请日：2022-07-27

申请人： United Microelectronics Corp.

发明人： Shun-Yu Huang ,  Yi-Wei Tseng ,  Chih-Wei Kuo ,  Yi-Xiang Chen ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC分类号： H01L43/12 ,  H01L27/222 ,  H01L43/02

摘要： A method of fabricating an MTJ device is provided including the following process. A first via is formed in the first dielectric layer. A first electrode layer is formed on the first dielectric layer and the first via. An MTJ stack layer is formed on the first electrode layer. A patterned second electrode layer is formed on the MTJ stack layer and used as a mask. A first ion beam etching process is performed to etch the patterned second electrode layer and pattern the MTJ stack layer and the first electrode layer to form a second electrode, an MTJ stack structure, and a first electrode. A first protective layer is formed to cover the second electrode and the MTJ stack structure. A second ion beam etching process is performed to remove a portion of the MTJ stack structure and a portion of the first electrode.

公开(公告)号：US11527710B2

公开(公告)日：2022-12-13

申请号：US16529779

申请日：2019-08-01

申请人： UNITED MICROELECTRONICS CORP.

发明人： Pei-Jou Lee ,  Kun-Chen Ho ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

摘要： A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.

公开(公告)号：US20150214068A1

公开(公告)日：2015-07-30

申请号：US14162755

申请日：2014-01-24

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen

IPC分类号： H01L21/311 ,  H01L21/027

CPC分类号： H01L21/31144 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/76816

摘要： A method of performing an etching process is provided. A substrate is provided, wherein a first region and a second region are defined on the substrate, and an overlapping region of the first region and the second region is defined as a third region. A tri-layer structure comprising an organic layer, a bottom anti-reflection coating (BARC), and a photoresist layer is formed on the substrate. The photoresist layer and the BARC in the second region are removed. An etching process is performed to remove the organic layer in the second region by using the BARC and/or the photoresist layer as a mask, wherein the etching process uses an etchant comprises CO2.

摘要翻译： 提供了一种执行蚀刻工艺的方法。 提供了一种衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 在基板上形成包括有机层，底部防反射涂层（BARC）和光致抗蚀剂层的三层结构。 去除第二区域中的光致抗蚀剂层和BARC。 通过使用BARC和/或光致抗蚀剂层作为掩模，进行蚀刻工艺以去除第二区域中的有机层，其中蚀刻工艺使用蚀刻剂包括CO 2。

公开(公告)号：US20140349236A1

公开(公告)日：2014-11-27

申请号：US13899577

申请日：2013-05-22

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chieh-Te Chen ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen ,  Feng-Yi Chang

IPC分类号： G03F7/22

CPC分类号： H01L21/28 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76816

摘要： A method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. A pattern density of the first region is substantially greater than that of the second region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.

摘要翻译： 提供一种形成具有开口的半导体结构的方法。 首先，提供衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 第一区域的图案密度基本上大于第二区域的图案密度。 然后，在基板上形成材料层。 第一硬掩模和第二硬掩模形成在材料层上。 第一区域中的第一硬掩模被去除以形成图案化的第一硬掩模。 去除第三区域中的第二硬掩模以形成图案化的第二硬掩模。 最后，通过使用图案化的第二硬掩模层作为掩模来对材料层进行图案化，以仅在第三区域中形成至少一个开口。