公开(公告)号：US11289489B2

公开(公告)日：2022-03-29

申请号：US16812384

申请日：2020-03-09

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chieh-Te Chen

IPC分类号： H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L49/02

摘要： A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.

公开(公告)号：US11244948B2

公开(公告)日：2022-02-08

申请号：US16158317

申请日：2018-10-12

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Ching Chang ,  Kai-Lou Huang

IPC分类号： H01L27/108

摘要： A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

公开(公告)号：US20210327706A1

公开(公告)日：2021-10-21

申请号：US17359634

申请日：2021-06-27

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Fu-Che Lee ,  Yu-Cheng Tung

IPC分类号： H01L21/027 ,  H01L21/033 ,  G03F7/26 ,  H01L27/108 ,  G03F7/16 ,  G03F7/20

摘要： A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.

公开(公告)号：US11139243B2

公开(公告)日：2021-10-05

申请号：US16446590

申请日：2019-06-19

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC分类号： H01L23/52 ,  H01L23/528 ,  H01L21/311 ,  H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L29/06

摘要： A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US11081353B2

公开(公告)日：2021-08-03

申请号：US16174237

申请日：2018-10-29

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Fu-Che Lee ,  Yu-Cheng Tung

IPC分类号： H01L21/027 ,  H01L21/033 ,  G03F7/26 ,  H01L27/108 ,  G03F7/16 ,  G03F7/20

摘要： A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.

公开(公告)号：US10795255B2

公开(公告)日：2020-10-06

申请号：US16175858

申请日：2018-10-31

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Wei-Lun Hsu ,  Gang-Yi Lin ,  Yu-Hsiang Hung ,  Ying-Chih Lin ,  Feng-Yi Chang ,  Ming-Te Wei ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chia-Liang Liao

IPC分类号： G03F1/36 ,  H01L23/538 ,  G03F1/38 ,  H01L21/033 ,  H01L21/308 ,  G03F1/00 ,  G03F7/20 ,  G03F7/00 ,  H01L27/108

摘要： A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.

公开(公告)号：US10784334B2

公开(公告)日：2020-09-22

申请号：US16129782

申请日：2018-09-12

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Fu-Che Lee

IPC分类号： H01L27/00 ,  H01L49/02 ,  H01L27/108

摘要： The present invention discloses a method of manufacturing a capacitor, which includes the steps of forming a capacitor recess in a sacrificial layer, wherein the sidewall of capacitor recess has a wave profile, forming a bottom electrode layer on the sidewall of capacitor recess, filling up the capacitor recess with a supporting layer, removing the sacrificial layer to forma capacitor pillar made up by the bottom electrode layer and the supporting layer, forming a capacitor dielectric layer on the capacitor pillar, and forming a top electrode layer on the capacitor dielectric layer.

公开(公告)号：US10658178B2

公开(公告)日：2020-05-19

申请号：US16024907

申请日：2018-07-01

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/027 ,  H01L27/108

摘要： A method of forming a capacitor mask includes the following steps. A bulk mandrel and a plurality of strip mandrels are formed on a mask layer. Spacers are formed on sidewalls of the bulk mandrel and the strip mandrels. The strip mandrels are removed while the bulk mandrel is reserved. A material fills in space between the spacers and on the bulk mandrel, wherein the material has a flat top surface. A patterned photoresist is formed to cover the bulk mandrel and a part of the spacers but exposing the other part of the spacers after filling the material.

公开(公告)号：US10658173B2

公开(公告)日：2020-05-19

申请号：US16039284

申请日：2018-07-18

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen ,  Ching-Pin Hsu

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/3065 ,  H01L27/108

摘要： A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.

公开(公告)号：US10600749B2

公开(公告)日：2020-03-24

申请号：US16505724

申请日：2019-07-09

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Fu-Che Lee ,  Chin-Hsin Chiu

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L21/66 ,  H01L23/525 ,  H01L23/62 ,  H01L23/532 ,  H01L23/485 ,  H01L23/528 ,  H01L21/311 ,  H01L23/31

摘要： A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.