公开(公告)号：US20140315365A1

公开(公告)日：2014-10-23

申请号：US13866456

申请日：2013-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chiang Chen ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai ,  Ching-Pin Hsu

IPC: H01L29/423 ,  H01L29/66

CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。

公开(公告)号：US09799550B2

公开(公告)日：2017-10-24

申请号：US14845294

申请日：2015-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hao Huang ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai

IPC: H01L21/02 ,  H01L21/441 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/41791 ,  H01L2029/7858

Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.

公开(公告)号：US20140038399A1

公开(公告)日：2014-02-06

申请号：US14054839

申请日：2013-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

IPC: H01L21/308

CPC classification number: H01L21/308 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816

Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask. Before forming the hard mask, a gate which includes a contact etch stop layer and a dielectric layer is formed on the semiconductor substrate.

Abstract translation: 公开了一种制造孔的方法。 该方法包括以下步骤：在半导体衬底的表面上形成含有碳的硬掩模; 并且使用含有气体的非氧元素进行用于在硬掩模中形成第一孔的第一蚀刻工艺。 在形成硬掩模之前，在半导体衬底上形成包括接触蚀刻停止层和电介质层的栅极。

公开(公告)号：US09337084B1

公开(公告)日：2016-05-10

申请号：US14846822

申请日：2015-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Kun-Yuan Liao ,  Chun-Lung Chen ,  Ching-Pin Hsu ,  Shang-Yuan Tsai

IPC: H01L21/768 ,  H01L27/11

CPC classification number: H01L21/76816 ,  H01L21/76801 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

Abstract: The present invention provides a method for manufacturing contact holes of a semiconductor device, including a first dielectric layer is provided, a first region and a second region are defined on the first dielectric layer respectively, at least two cutting hard masks are formed and disposed within the first region and the second region respectively, at least two step-height portions disposed right under the cutting hard masks respectively. Afterwards, at least one first slot opening within the first region is formed, where the first slot opening partially overlaps the cutting hard mask and directly contacts the cutting hard mask, and at least one second contact opening is formed within the second region, where the second contact opening does not contact the cutting hard mask directly, and at least two contact holes are formed, where each contact hole penetrates through each step height portion.

Abstract translation: 本发明提供了一种用于制造半导体器件的接触孔的方法，包括第一介电层，第一介电层和第二区分别形成在第一介电层上，形成至少两个切割硬掩模， 第一区域和第二区域分别设置在切割硬掩模正下方的至少两个台阶部分。 之后，形成在第一区域内的至少一个第一狭槽开口，其中第一狭槽开口部分地与切割硬掩模重叠并且直接接触切割硬掩模，并且在第二区域内形成至少一个第二接触开口， 第二接触开口不直接接触切割硬掩模，并且形成至少两个接触孔，其中每个接触孔穿过每个台阶高度部分。

公开(公告)号：US20170069528A1

公开(公告)日：2017-03-09

申请号：US14845294

申请日：2015-09-04

Applicant: United Microelectronics Corp.

Inventor： Wei-Hao Huang ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/41791 ,  H01L2029/7858

Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.

Abstract translation: 本发明提供一种形成开口的方法，包括：首先在目标层上形成硬掩模材料层，接着在硬掩模材料层上形成三层硬掩模，其中三层硬 掩模包括底部有机层（ODL），中间含硅硬掩模底部防反射涂层（SHB）层和顶部光致抗蚀剂层，然后进行蚀刻工艺以除去三层硬掩模的部分 ，硬掩模材料层的一部分和目标层的一部分，以便在目标层中形成至少一个开口，其中在用于去除硬掩模材料层的部分的步骤期间，侧面蚀刻速率为 硬掩模材料层小于ODL的横向蚀刻速率。

公开(公告)号：US09023708B2

公开(公告)日：2015-05-05

申请号：US13866456

申请日：2013-04-19

Applicant: United Microelectronics Corp.

Inventor： Li-Chiang Chen ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai ,  Ching-Pin Hsu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。