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公开(公告)号：US20220130903A1
公开(公告)日：2022-04-28
申请号：US17571519
申请日：2022-01-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.
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公开(公告)号：US10707225B2
公开(公告)日：2020-07-07
申请号：US16792847
申请日：2020-02-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
IPC: H01L27/115 , H01L27/11568 , H01L29/792 , H01L21/28
Abstract: A method for fabricating a semiconductor memory device is disclosed. A substrate having a main surface is provided. A memory gate is formed on the main surface of the substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is formed in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is formed between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is formed on the first sidewall of the memory gate and a second single spacer structure on the fourth sidewall of the control gate. A gap-filling layer is formed to fill up the gap.
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公开(公告)号：US12127488B2
公开(公告)日：2024-10-22
申请号：US17876560
申请日：2022-07-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H10N70/8833 , H10B63/80 , H10N70/021 , H10N70/063 , H10N70/066 , H10N70/841
Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.
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公开(公告)号：US12041863B2
公开(公告)日：2024-07-16
申请号：US17159160
申请日：2021-01-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H10N70/8833 , H10B63/00 , H10N70/023 , H10N70/063 , H10N70/841
Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming said resistive random access memory (RRAM) structure is also provided.
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公开(公告)号：US11950521B2
公开(公告)日：2024-04-02
申请号：US17741471
申请日：2022-05-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shu-Hung Yu , Chun-Hung Cheng , Chuan-Fu Wang
IPC: H10N70/00
CPC classification number: H10N70/826 , H10N70/063 , H10N70/841 , H10N70/8833
Abstract: A resistive random-access memory (RRAM) device includes a bottom electrode, a high work function layer, a resistive material layer, a top electrode and high work function spacers. The bottom electrode, the high work function layer, the resistive material layer and the top electrode are sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part. The high work function spacers cover sidewalls of the bottom part, thereby constituting a RRAM cell. The present invention also provides a method of forming a RRAM device.
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Patent Agency Ranking
公开(公告)号：US20240107901A1
公开(公告)日：2024-03-28
申请号：US18528826
申请日：2023-12-05
Applicant: United Microelectronics Corp.
Inventor： Kai Jiun Chang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H10N70/828 , H10N70/023 , H10N70/063 , H10N70/24 , H10N70/841 , H10N70/8833 , H10N70/8836
Abstract: Provided is a resistive random access memory (RRAM). The resistive random access memory includes a plurality of unit structures disposed on a substrate. Each of the unit structures includes a first electrode, and a first metal oxide layer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. In addition, the resistive random access memory includes a second electrode. The second electrode is disposed on the plurality of unit structures and connected to the plurality of unit structures.
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公开(公告)号：US20240074338A1
公开(公告)日：2024-02-29
申请号：US18503140
申请日：2023-11-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H10N70/8833 , H10B63/00 , H10N70/023 , H10N70/063 , H10N70/841
Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.
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公开(公告)号：US20230413698A1
公开(公告)日：2023-12-21
申请号：US17876560
申请日：2022-07-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H01L45/146 , H01L45/1253 , H01L45/1675 , H01L45/1683 , H01L45/1608 , H01L27/2463
Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.
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公开(公告)号：US20220399495A1
公开(公告)日：2022-12-15
申请号：US17378795
申请日：2021-07-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
IPC: H01L45/00
Abstract: A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.
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公开(公告)号：US11233196B2
公开(公告)日：2022-01-25
申请号：US16687297
申请日：2019-11-18
Applicant: United Microelectronics Corp.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
IPC: H01L45/00
Abstract: A memory device structure includes a substrate, a memory stacked structure, and a spacer. The memory stacked structure is formed on the substrate by stacking a first electrode layer, a memory material layer, and a second electrode layer. The memory material layer has a tilted sidewall, or the memory material layer and the first electrode layer have a tilted sidewall. The tilted sidewall is indented with respect to a sidewall of the second electrode layer. The spacer is disposed on the tilted sidewall.
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