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公开(公告)号：US11895933B2
公开(公告)日：2024-02-06
申请号：US17855155
申请日：2022-06-30
发明人： Fa-Shen Jiang , Cheng-Yuan Tsai , Hai-Dang Trinh , Hsing-Lien Lin , Hsun-Chung Kuang , Bi-Shen Lee
CPC分类号： H10N70/828 , H10B63/30 , H10N70/043 , H10N70/063 , H10N70/24 , H10N70/8833
摘要： Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.
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公开(公告)号：US11758830B2
公开(公告)日：2023-09-12
申请号：US17324328
申请日：2021-05-19
发明人： Hai-Dang Trinh , Hsing-Lien Lin , Cheng-Yuan Tsai
CPC分类号： H10N70/828 , H10N70/063 , H10N70/24 , H10N70/245 , H10N70/801 , H10N70/826 , H10N70/841 , H10N70/8833
摘要： A semiconductor device structure is provided. The structure includes a semiconductor substrate and a data storage element over the semiconductor substrate. The structure also includes an ion diffusion barrier element over the data storage element and a protective element extending along a sidewall of the ion diffusion barrier element. A bottom surface of the protective element is between a top surface of the data storage element and a bottom surface of the data storage element. The structure further includes a first electrode electrically connected to the data storage element and a second electrode electrically connected to the data storage element.
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公开(公告)号：US11723292B2
公开(公告)日：2023-08-08
申请号：US16910609
申请日：2020-06-24
发明人： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
CPC分类号： H10N70/8265 , H10B63/30 , H10N70/011 , H10N70/063 , H10N70/066 , H10N70/20 , H10N70/24 , H10N70/826 , H10N70/841 , H10N70/8833 , H10N70/021 , H10N70/023 , H10N70/026 , H10N70/028 , H10N70/041 , H10N70/043 , H10N70/046 , H10N70/061 , H10N70/068 , H10N70/231 , H10N70/235 , H10N70/245 , H10N70/25 , H10N70/253 , H10N70/257 , H10N70/801 , H10N70/821 , H10N70/823 , H10N70/828 , H10N70/8413 , H10N70/8416 , H10N70/8418 , H10N70/8613 , H10N70/8616 , H10N70/881 , H10N70/882 , H10N70/883 , H10N70/884 , H10N70/8822 , H10N70/8825 , H10N70/8828 , H10N70/8836 , H10N70/8845
摘要： The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.
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公开(公告)号：US20240237561A9
公开(公告)日：2024-07-11
申请号：US18493921
申请日：2023-10-25
CPC分类号： H10N70/828 , H10B63/30 , H10N70/063 , H10N70/24 , H10N70/826 , H10N70/841
摘要： A resistive memory device including at least one first electrode based on a first metal and a second electrode based on a second metal, and a memory element in the form of a metal filament based on a third metal and inserted between the first and second electrodes, the memory element having a filament cross-section strictly smaller than the electrode cross-sections, wherein the third metal has a chemical composition, different from those of the first and second metals giving it an etching speed greater than those of the first and second metals, preferably such that the selectivity at the etching is greater than or equal to 3:1, vis-á-vis the first and second metals. A method for manufacturing such a device is also disclosed.
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公开(公告)号：US11991937B2
公开(公告)日：2024-05-21
申请号：US17839693
申请日：2022-06-14
发明人： Hai-Dang Trinh , Hsing-Lien Lin , Fa-Shen Jiang
CPC分类号： H10N70/245 , H10N70/011 , H10N70/24 , H10N70/826 , H10N70/828 , H10N70/8416
摘要： A semiconductor device includes a bottom electrode, a top electrode over the bottom electrode, a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data, a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer, an ion reservoir region formed in the capping layer, a diffusion barrier layer between the bottom electrode and the switching layer, wherein the diffusion barrier layer includes palladium (Pd), cobalt (Co), or a combination thereof and is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion layer has a concaved top surface, and a passivation layer covering a portion of the top electrode, and wherein the passivation layer directly contacts a top surface of the switching layer.
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公开(公告)号：US20240138273A1
公开(公告)日：2024-04-25
申请号：US18493921
申请日：2023-10-24
CPC分类号： H10N70/828 , H10B63/30 , H10N70/063 , H10N70/24 , H10N70/826 , H10N70/841
摘要： A resistive memory device including at least one first electrode based on a first metal and a second electrode based on a second metal, and a memory element in the form of a metal filament based on a third metal and inserted between the first and second electrodes, the memory element having a filament cross-section strictly smaller than the electrode cross-sections, wherein the third metal has a chemical composition, different from those of the first and second metals giving it an etching speed greater than those of the first and second metals, preferably such that the selectivity at the etching is greater than or equal to 3:1, vis-á-vis the first and second metals. A method for manufacturing such a device is also disclosed.
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公开(公告)号：US11937522B2
公开(公告)日：2024-03-19
申请号：US17315996
申请日：2021-05-10
发明人： Dexin Kong , Takashi Ando , Kangguo Cheng , Juntao Li
CPC分类号： H10N70/828 , H10N70/826 , H10N70/8418 , H10N70/883 , H10N70/8833 , H10N70/023 , H10N70/026 , H10N70/061 , H10N70/24
摘要： A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.
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8.发明公开公开(公告)号：US20240057347A1
公开(公告)日：2024-02-15
申请号：US18348846
申请日：2023-07-07
发明人： Wooyoung YANG , Hyungjun Kim , Hajun Sung , Kiyeon Yang , Changseung Lee , Changyup Park , Seung-min Chung , Sangyoon Lee , Inkyu Sohn
CPC分类号： H10B63/10 , H10N70/231 , H10N70/8822 , H10N70/826 , H10N70/828 , H10B63/20 , H10N70/023 , H10N70/8825
摘要： A memory element includes a substrate, a first electrode formed on the substrate, a phase-change heterolayer formed on the first electrode and electrically connected to the first electrode, and a second electrode formed on the phase-change heterolayer, wherein the phase-change heterolayer includes one or more confinement material layers and one or more phase-change material layers, and the confinement material layer includes a metal chalcogenide film.
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公开(公告)号：US11889776B2
公开(公告)日：2024-01-30
申请号：US17356029
申请日：2021-06-23
发明人： Ryutaro Yasuhara , Satoru Fujii , Takumi Mikawa , Atsushi Himeno , Kengo Nishio , Takehide Miyazaki , Hiroyuki Akinaga , Yasuhisa Naitoh , Hisashi Shima
CPC分类号： H10N70/828 , H10B63/20 , H10B63/30 , H10N70/24
摘要： A variable resistance non-volatile memory element includes first and second electrodes and a variable resistance layer between the electrodes. The layer has a resistance value reversibly variable based on an electrical signal. The layer includes a first variable resistance layer that includes an oxygen deficient first metal oxide containing a first metal element and oxygen, and a second variable resistance layer that includes a composite oxide containing the first metal element, a second metal element different from the first metal element, and oxygen, and having a different degree of oxygen deficiency from the first metal oxide. The composite oxide has a lower degree of oxygen deficiency than the first metal oxide. At room temperature, the composite oxide has a smaller oxygen diffusion coefficient than a second metal oxide containing the first metal element and oxygen, and having the degree of oxygen deficiency equal to that of the composite oxide.
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10.发明公开公开(公告)号：US20230144512A1
公开(公告)日：2023-05-11
申请号：US18052921
申请日：2022-11-06
发明人： Yu LIU , Tingying SHEN , SZU-CHUN KANG , Taiwei CHIU , Danyun WANG , Lijun SHAN
CPC分类号： H10N70/828 , H10B63/80 , H10N70/24 , H10N70/063
摘要： The present disclosure discloses a method for manufacturing a resistive switching element, including: performing an etching process, a deposition process and a polishing process alternately to prepare the bottom electrode, the resistive switching layer and the top electrode; and optimizing at least one of the bottom electrode, the resistive switching materials and the oxygen storage layer by using the sidewall process when preparing the bottom electrode and the resistive switching materials, so as to reduce a contact area between the bottom electrode and the resistive switching materials, and/or reduce a contact area between the resistive switching materials and the oxygen storage layer. The method could form conductive filaments in the resistive switching layer, and a low resistive state and high resistive state are realized by forming and breaking conductive filaments. The present disclosure further discloses a resistive switching element and a resistive switching memory having the resistive switching element.
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