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公开(公告)号：US10978457B2
公开(公告)日：2021-04-13
申请号：US16177413
申请日：2018-10-31
Inventor： Li-Wei Feng , Yu-Hsiang Hung , Ming-Te Wei
IPC: H01L27/108 , H01L23/532
Abstract: The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.
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公开(公告)号：US10068907B1
公开(公告)日：2018-09-04
申请号：US15593338
申请日：2017-05-12
Inventor： Tsung-Ying Tsai , Chien-Ting Ho , Ming-Te Wei , Li-Wei Feng , Ying-Chiao Wang
IPC: H01L23/528 , H01L27/108 , H01L29/06
Abstract: A dynamic random access memory (DRAM) includes a substrate, two buried word lines and a bit line contact. The substrate includes a first active area, wherein the first active area extends along a first direction. The buried word lines are disposed in the substrate and across the first active area, wherein the buried word lines extend along a second direction. The bit line contact is disposed on the substrate and overlaps the first active area between the two buried word lines, wherein the bit line contact is enclosed by a first side, a second side, a third side and a fourth side, and the first side is parallel to the third side along a third direction while the second side is parallel to the fourth side along a fourth direction, wherein the third direction is parallel to the first direction and the fourth direction is parallel to the second direction.
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公开(公告)号：US09299843B2
公开(公告)日：2016-03-29
申请号：US14078701
申请日：2013-11-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jun-Jie Wang , Po-Chao Tsao , Ming-Te Wei , Shih-Fang Tzou
CPC classification number: H01L29/785 , H01L29/66795
Abstract: A semiconductor structure comprises a substrate, a plurality of fins, an oxide layer and a gate structure. The fins protrude from the substrate and are separated from each other by the oxide layer. The surface of the oxide layer is uniform and even plane. The gate structure is disposed on the fins. The fin height is distance between the top of the fins and the oxide layer, and at least two of the fins have different fin heights.
Abstract translation: 半导体结构包括基板，多个翅片，氧化物层和栅极结构。 翅片从衬底突出并且通过氧化物层彼此分离。 氧化物层的表面均匀均匀。 栅极结构设置在翅片上。 翅片高度是翅片的顶部和氧化物层之间的距离，并且至少两个翅片具有不同的翅片高度。
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公开(公告)号：US09141744B2
公开(公告)日：2015-09-22
申请号：US13968391
申请日：2013-08-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Chao Tsao , Shih-Fang Hong , Chia-Wei Huang , Ming-Jui Chen , Shih-Fang Tzou , Ming-Te Wei
CPC classification number: G06F17/5068 , G03F1/144 , G03F1/36
Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.
Abstract translation: 提供了一种用于生成布局图案的方法。 首先，将布局图案提供给计算机系统，并将其分为两个子图案和空白图案。 每个子图案具有简单整数比例的间距，并且空白图案在两个子图案之间。 然后，生成多个第一条纹图案和至少两个第二条纹图案。 第一条形图案的边缘与子图案的边缘对齐，并且第一条纹图案具有相等的间隔和宽度。 第二条纹图案的间距或宽度与第一条纹图案的间距或宽度不同。
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公开(公告)号：US09048246B2
公开(公告)日：2015-06-02
申请号：US13921174
申请日：2013-06-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ming-Te Wei , Po-Chao Tsao , Ching-Li Yang , Chien-Yang Chen , Hui-Ling Chen , Guan-Kai Huang
IPC: H01L23/00 , H01L21/768 , H01L21/78 , H01L23/58
CPC classification number: H01L23/562 , H01L21/76838 , H01L21/78 , H01L23/585 , H01L2924/0002 , H01L2924/00
Abstract: A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.
Abstract translation: 提供了模具密封环。 模具密封环包括基材和从基材挤出的第一层。 第一层具有第一鳍环结构，并且第一鳍环结构的布局具有戳状形状。 此外，提供了一种用于形成模具密封环的方法。 提供具有有源区的衬底。 在衬底上形成图案化的牺牲层。 在图案化牺牲层的侧壁上形成间隔物。 图案化的牺牲层被去除。 通过使用间隔物作为掩模对衬底进行构图，从而同时形成Fin-FET的鳍结构和模密封环的第一层。
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Patent Agency Ranking
公开(公告)号：US20150129980A1
公开(公告)日：2015-05-14
申请号：US14078701
申请日：2013-11-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jun-Jie Wang , Po-Chao Tsao , Ming-Te Wei , Shih-Fang Tzou
CPC classification number: H01L29/785 , H01L29/66795
Abstract: A semiconductor structure comprises a substrate, a plurality of fins, an oxide layer and a gate structure. The fins protrude from the substrate and are separated from each other by the oxide layer. The surface of the oxide layer is uniform and even plane. The gate structure is disposed on the fins. The fin height is distance between the top of the fins and the oxide layer, and at least two of the fins have different fin heights.
Abstract translation: 半导体结构包括基板，多个翅片，氧化物层和栅极结构。 翅片从衬底突出并且通过氧化物层彼此分离。 氧化物层的表面均匀均匀。 栅极结构设置在翅片上。 翅片高度是翅片的顶部和氧化物层之间的距离，并且至少两个翅片具有不同的翅片高度。
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公开(公告)号：US20210193668A1
公开(公告)日：2021-06-24
申请号：US17194324
申请日：2021-03-08
Inventor： Li-Wei Feng , Yu-Hsiang Hung , Ming-Te Wei
IPC: H01L27/108
Abstract: The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.
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公开(公告)号：US20200105764A1
公开(公告)日：2020-04-02
申请号：US16175858
申请日：2018-10-31
Inventor： Wei-Lun Hsu , Gang-Yi Lin , Yu-Hsiang Hung , Ying-Chih Lin , Feng-Yi Chang , Ming-Te Wei , Shih-Fang Tzou , Fu-Che Lee , Chia-Liang Liao
IPC: H01L27/108 , G11C11/402 , H01L23/538
Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
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公开(公告)号：US20200035782A1
公开(公告)日：2020-01-30
申请号：US16116859
申请日：2018-08-29
Inventor： Li-Wei Feng , En-Chiuan Liou , Yu-Cheng Tung , Wei-Lun Hsu , Yu-Hsiang Hung , Ming-Te Wei , Le-Tien Jung
Abstract: The present invention provides a semiconductor structure including a substrate including a plurality of capacitor lower electrodes, the capacitor lower electrodes are arranged in a diamond array along a first direction and a second direction respectively, the first direction and the second direction are not perpendicular to each other. A supporting structure layer contacts at least parts of the capacitor lower electrodes, wherein the supporting structure layer includes a plurality of triangular openings, and the three corners of each triangular opening are overlapped with three adjacent capacitor lower electrodes respectively.
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公开(公告)号：US10475648B1
公开(公告)日：2019-11-12
申请号：US15968680
申请日：2018-05-01
Inventor： Li-Wei Feng , Ming-Te Wei , Yu-Chieh Lin , Ying-Chiao Wang , Chien-Ting Ho
IPC: H01L21/033 , H01L21/02 , H01L27/108 , H01L21/027 , H01L21/3105 , H01L21/311
Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.
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