公开(公告)号：US20250015174A1

公开(公告)日：2025-01-09

申请号：US18888145

申请日：2024-09-17

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yung-Fong Lin ,  Yu-Chieh Chou ,  Tsung-Hsiang Lin ,  Li-Wen Chuang

IPC: H01L29/778 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/47 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

公开(公告)号：US20240321626A1

公开(公告)日：2024-09-26

申请号：US18677824

申请日：2024-05-29

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yang Du ,  Yung-Fong Lin ,  Tsung-Hsiang Lin ,  Yu-Chieh Chou ,  Cheng-Tao Chou ,  Yi-Chun Lu ,  Chun-Hsu Chen

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L27/12

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

公开(公告)号：US11955397B2

公开(公告)日：2024-04-09

申请号：US17092851

申请日：2020-11-09

Applicant: Vanguard International Semiconductor Corporation

Inventor： Shin-Cheng Lin ,  Cheng-Wei Chou ,  Ting-En Hsieh ,  Yi-Han Huang ,  Kwang-Ming Lin ,  Yung-Fong Lin ,  Cheng-Tao Chou ,  Chi-Fu Lee ,  Chia-Lin Chen ,  Shu-Wen Chang

IPC: H01L29/778 ,  H01L23/31 ,  H01L29/66 ,  H01L21/02 ,  H01L23/29 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L23/3192 ,  H01L23/3171 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L21/0206 ,  H01L23/291 ,  H01L29/2003 ,  H01L29/205

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

公开(公告)号：US20210336016A1

公开(公告)日：2021-10-28

申请号：US16861191

申请日：2020-04-28

Applicant: Vanguard International Semiconductor Corporation

Inventor： Ting-En Hsieh ,  Yu-Chieh Chou ,  Yung-Fong Lin

IPC: H01L29/40 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/778 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.

公开(公告)号：US11011391B2

公开(公告)日：2021-05-18

申请号：US16502644

申请日：2019-07-03

Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION

Inventor： Yung-Fong Lin ,  Yu-Chieh Chou

IPC: H01L21/67 ,  H01L21/02

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate; forming a silicon layer on the substrate, wherein an edge region of the top surface of the substrate is exposed from the silicon layer; epitaxially growing a GaN-based semiconductor material on the silicon layer and the substrate to form a GaN-based semiconductor layer on the silicon layer and a plurality of GaN-based nodules on the edge region of the top surface of the substrate; and performing a first dry etch step to remove the GaN-based nodules, wherein performing the first dry etch step includes applying a first bias power that is equal to or higher than 1500 W.

公开(公告)号：US20220293747A1

公开(公告)日：2022-09-15

申请号：US17827809

申请日：2022-05-30

Applicant: Vanguard International Semiconductor Corporation

Inventor： Ting-En Hsieh ,  Yu-Chieh Chou ,  Yung-Fong Lin

IPC: H01L29/40 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L29/778

Abstract: A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.

公开(公告)号：US11380767B2

公开(公告)日：2022-07-05

申请号：US16861191

申请日：2020-04-28

Applicant: Vanguard International Semiconductor Corporation

Inventor： Ting-En Hsieh ,  Yu-Chieh Chou ,  Yung-Fong Lin

IPC: H01L29/778 ,  H01L29/40 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

Abstract: A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.

公开(公告)号：US11049799B1

公开(公告)日：2021-06-29

申请号：US16824134

申请日：2020-03-19

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yung-Fong Lin ,  Shin-Cheng Lin ,  Cheng-Wei Chou ,  Yu-Chieh Chou

IPC: H01L23/48 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8232 ,  H01L29/778 ,  H01L29/06 ,  H01L27/085

Abstract: A semiconductor structure and a method for forming the same are provided. A semiconductor structure includes a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, a first transistor on the epitaxial layer, an interlayer dielectric layer on the epitaxial layer, a dielectric pillar penetrating through the interlayer dielectric layer and the epitaxial layer, and a conductive liner disposed on a sidewall of the dielectric pillar. The conductive liner is electrically connected to the first transistor and the seed layer.

公开(公告)号：US10971355B2

公开(公告)日：2021-04-06

申请号：US16690408

申请日：2019-11-21

Applicant: Vanguard International Semiconductor Corporation

Inventor： Kwang-Ming Lin ,  Yung-Fong Lin

IPC: H01L21/02 ,  H01L29/205

Abstract: A substrate includes a ceramic core, a first adhesion layer, a barrier layer, and a second adhesion layer. The first adhesion layer encapsulates the ceramic core and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the first adhesion layer has a first ratio. The barrier layer encapsulates the first adhesion layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the barrier layer has a second ratio that is different from the first ratio. The second adhesion layer encapsulates the barrier layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the second adhesion layer has a third ratio that is different from the second ratio.