公开(公告)号：US11552171B2

公开(公告)日：2023-01-10

申请号：US17501336

申请日：2021-10-14

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yung-Fong Lin ,  Cheng-Tao Chou

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from −20 μm to −40 μm.

公开(公告)号：US20220336649A1

公开(公告)日：2022-10-20

申请号：US17231032

申请日：2021-04-15

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yung-Fong Lin ,  Yu-Chieh Chou ,  Tsung-Hsiang Lin ,  Li-Wen Chuang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/47 ,  H01L21/285 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

公开(公告)号：US12132103B2

公开(公告)日：2024-10-29

申请号：US17231032

申请日：2021-04-15

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yung-Fong Lin ,  Yu-Chieh Chou ,  Tsung-Hsiang Lin ,  Li-Wen Chuang

IPC: H01L29/778 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/47 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66462

Abstract: A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

公开(公告)号：US12027413B2

公开(公告)日：2024-07-02

申请号：US17408471

申请日：2021-08-22

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yang Du ,  Yung-Fong Lin ,  Tsung-Hsiang Lin ,  Yu-Chieh Chou ,  Cheng-Tao Chou ,  Yi-Chun Lu ,  Chun-Hsu Chen

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L27/12

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

公开(公告)号：US20230058295A1

公开(公告)日：2023-02-23

申请号：US17408471

申请日：2021-08-22

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yang Du ,  Yung-Fong Lin ,  Tsung-Hsiang Lin ,  Yu-Chieh Chou ,  Cheng-Tao Chou ,  Yi-Chun Lu ,  Chun-Hsu Chen

IPC: H01L21/762 ,  H01L27/12

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

公开(公告)号：US11955522B2

公开(公告)日：2024-04-09

申请号：US16789682

申请日：2020-02-13

Applicant: Vanguard International Semiconductor Corporation

Inventor： Cheng-Wei Chou ,  Shin-Cheng Lin ,  Yung-Fong Lin

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/285 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/408 ,  H01L21/0217 ,  H01L21/02186 ,  H01L21/28575 ,  H01L23/291 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a source structure, and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure are disposed on the passivation layer.

公开(公告)号：US11929407B2

公开(公告)日：2024-03-12

申请号：US17827809

申请日：2022-05-30

Applicant: Vanguard International Semiconductor Corporation

Inventor： Ting-En Hsieh ,  Yu-Chieh Chou ,  Yung-Fong Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/47 ,  H01L29/778

CPC classification number: H01L29/408 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/28581 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.

公开(公告)号：US11211331B2

公开(公告)日：2021-12-28

申请号：US16749335

申请日：2020-01-22

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yung-Fong Lin ,  Li-Wen Chuang ,  Jui-Hung Yu ,  Cheng-Tao Chou ,  Chun-Hsu Chen ,  Yu-Chieh Chou

IPC: H01L23/535 ,  H01L21/74 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.

公开(公告)号：US11183563B2

公开(公告)日：2021-11-23

申请号：US16593208

申请日：2019-10-04

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yung-Fong Lin ,  Cheng-Tao Chou

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from −20 μm to −40 μm.

公开(公告)号：US10790143B1

公开(公告)日：2020-09-29

申请号：US16502711

申请日：2019-07-03

Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION

Inventor： Yung-Fong Lin ,  Cheng-Tao Chou

IPC: H01L21/02 ,  H01L29/20 ,  H01L33/00 ,  H01L29/205 ,  H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L33/12 ,  H01L33/20 ,  H01L33/32

Abstract: A semiconductor structure, a high electron mobility transistor (HEMT), and a method for fabricating a semiconductor structure are provided. The semiconductor structure includes a substrate, a flowable dielectric material pad layer, a reflow protection layer, and a GaN-based semiconductor layer. The substrate has a pit exposed from a top surface of the substrate. The flowable dielectric material pad layer is formed in the pit, and a top surface of the flowable dielectric material pad layer is below the top surface of the substrate. The reflow protection layer is formed on the substrate and the top surface of the flowable dielectric material pad layer. The GaN-based semiconductor layer is disposed over the substrate.