公开(公告)号：US20240321626A1

公开(公告)日：2024-09-26

申请号：US18677824

申请日：2024-05-29

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yang Du ,  Yung-Fong Lin ,  Tsung-Hsiang Lin ,  Yu-Chieh Chou ,  Cheng-Tao Chou ,  Yi-Chun Lu ,  Chun-Hsu Chen

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L27/12

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

公开(公告)号：US12027413B2

公开(公告)日：2024-07-02

申请号：US17408471

申请日：2021-08-22

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yang Du ,  Yung-Fong Lin ,  Tsung-Hsiang Lin ,  Yu-Chieh Chou ,  Cheng-Tao Chou ,  Yi-Chun Lu ,  Chun-Hsu Chen

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L27/12

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

公开(公告)号：US20230058295A1

公开(公告)日：2023-02-23

申请号：US17408471

申请日：2021-08-22

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yang Du ,  Yung-Fong Lin ,  Tsung-Hsiang Lin ,  Yu-Chieh Chou ,  Cheng-Tao Chou ,  Yi-Chun Lu ,  Chun-Hsu Chen

IPC: H01L21/762 ,  H01L27/12

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

公开(公告)号：US11211331B2

公开(公告)日：2021-12-28

申请号：US16749335

申请日：2020-01-22

Applicant: Vanguard International Semiconductor Corporation

Inventor： Yung-Fong Lin ,  Li-Wen Chuang ,  Jui-Hung Yu ,  Cheng-Tao Chou ,  Chun-Hsu Chen ,  Yu-Chieh Chou

IPC: H01L23/535 ,  H01L21/74 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.

公开(公告)号：US10431465B2

公开(公告)日：2019-10-01

申请号：US15707819

申请日：2017-09-18

Applicant: Vanguard International Semiconductor Corporation

Inventor： Chih-Ming Kao ,  Rong-Gen Wu ,  Han-Wen Chang ,  Chun-Hsu Chen ,  Yu-Chun Ho

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/761 ,  H01L29/40 ,  H01L21/3215

Abstract: A method of fabricating a semiconductor structure includes providing a semiconductor substrate, forming a trench in the semiconductor substrate, overfilling the trench with a first semiconductor material, wherein the first semiconductor material does not have a dopant, forming a second semiconductor material on the first semiconductor material, wherein the second semiconductor material contains a dopant, and performing a thermal treatment so that the dopant in the second semiconductor material diffuses into the first semiconductor material to form a doped third semiconductor material in the trench.