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11.发明申请REDUCING WRITE AMPLIFICATION IN A CACHE WITH FLASH MEMORY USED AS A WRITE CACHE 有权在使用闪存存储器的缓存中减少写入扩展公开(公告)号：US20110320687A1
公开(公告)日：2011-12-29
申请号：US12826499
申请日：2010-06-29
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0868 , G06F2212/2022 , G06F2212/282 , G06F2212/461
摘要： Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of memory pages. Data are buffered in a buffer. The data includes data to be cached, and data to be destaged from the cache to a storage subsystem. Data to be cached are written from the buffer to the at least one flash memory device. A processor coupled to the buffer is provided with access to the data written to the at least one flash memory device from the buffer, and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The data written to the at least one flash memory device are destaged from the buffer to the storage subsystem.
摘要翻译： 本发明的实施例旨在减少用作写入高速缓存的闪存的高速缓存中的写入放大。 本发明的实施例包括将高速缓存中的至少一个闪存设备划分成多个逻辑分区。 多个逻辑分区中的每一个是至少一个闪速存储器设备之一的逻辑细分，并且包括多个存储器页。 数据被缓冲在缓冲区中。 数据包括要缓存的数据以及要从高速缓存迁移到存储子系统的数据。 要缓存的数据从缓冲器写入至少一个闪速存储器件。 耦合到缓冲器的处理器提供对从缓冲器写入至少一个闪速存储器设备的数据的访问，以及写入多个逻辑分区内的至少一个闪存设备的数据的位置。 写入至少一个闪存设备的数据从缓冲器中迁移到存储子系统。
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12.发明申请METHOD OF CODE COVERAGE UTILIZING EFFICIENT DYNAMIC MUTATION OF LOGIC (EDML) 失效使用有效的动态动态变换（EDML）的代码覆盖方法公开(公告)号：US20090089771A1
公开(公告)日：2009-04-02
申请号：US11864322
申请日：2007-09-28
申请人： Binny S. Gill , Wendy A. Belluomini
发明人： Binny S. Gill , Wendy A. Belluomini
IPC分类号： G06F9/45
CPC分类号： G06F11/3616 , G06F11/3624
摘要： A method and computer program product for code coverage utilizing efficient dynamic mutation of logic (EDML) are provided. A source code is read, and instrumentation points are located. Self Modifying Code (SMC) is inserted at the instrumentation points producing instrumented code. Additional functions are inserted in the source code to enable read and/or reset of code coverage statistics. The instrumented code is compiled, and executables are run for a period of time during which zero or more instrumentation points are executed. In response to executing instrumentation points, instructions are executed to record execution of the instrumented code. Instructions of the instrumented code overwrite themselves at certain points so that a next execution of the instrumentation points skips over the instrumented code at the certain points. Code coverage statistics are gathered and recorded. The code coverage statistics are reset to begin another period of time for gathering code coverage statistics.
摘要翻译： 提供了一种使用有效的动态逻辑突变（EDML）进行代码覆盖的方法和计算机程序产品。 读取源代码，并找到检测点。 自动修改代码（SMC）被插入到产生检测代码的仪表点上。 在源代码中插入了附加功能，以实现代码覆盖统计信息的读取和/或复位。 已编制仪器化代码，并且可执行文件运行一段时间，在此期间执行零个或多个检测点。 响应执行的仪表点，执行指令以记录检测代码的执行。 仪器化代码的指令在某些点覆盖自己，以便下一次执行仪表点在特定点上跳过检测代码。 收集和记录代码覆盖率统计信息。 代码覆盖率统计信息被重置为开始另一个时间段来收集代码覆盖统计信息。
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13.发明授权Reducing write amplification in a cache with flash memory used as a write cache 有权在缓存中减少写入放大，闪存用作写缓存公开(公告)号：US08386714B2
公开(公告)日：2013-02-26
申请号：US12826499
申请日：2010-06-29
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0868 , G06F2212/2022 , G06F2212/282 , G06F2212/461
摘要： Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of memory pages. Data are buffered in a buffer. The data includes data to be cached, and data to be destaged from the cache to a storage subsystem. Data to be cached are written from the buffer to the at least one flash memory device. A processor coupled to the buffer is provided with access to the data written to the at least one flash memory device from the buffer, and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The data written to the at least one flash memory device are destaged from the buffer to the storage subsystem.
摘要翻译： 本发明的实施例旨在减少用作写入高速缓存的闪存的高速缓存中的写入放大。 本发明的实施例包括将高速缓存中的至少一个闪存设备划分成多个逻辑分区。 多个逻辑分区中的每一个是至少一个闪速存储器设备之一的逻辑细分，并且包括多个存储器页。 数据被缓冲在缓冲区中。 数据包括要缓存的数据以及要从高速缓存迁移到存储子系统的数据。 要缓存的数据从缓冲器写入至少一个闪速存储器件。 耦合到缓冲器的处理器提供对从缓冲器写入至少一个闪速存储器设备的数据的访问，以及写入多个逻辑分区内的至少一个闪存设备的数据的位置。 写入至少一个闪存设备的数据从缓冲器中迁移到存储子系统。
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14.发明申请COMPUTER PROGRAM PRODUCT OF CODE COVERAGE UTILIZING EFFICIENT DYNAMIC MUTATION OF LOGIC (EDML) 失效使用有效的动态动态变动（EDML）的计算机程序产品代码覆盖公开(公告)号：US20090089760A1
公开(公告)日：2009-04-02
申请号：US12057724
申请日：2008-03-28
申请人： Binny S. Gill , Wendy A. Belluomini
发明人： Binny S. Gill , Wendy A. Belluomini
IPC分类号： G06F9/44
CPC分类号： G06F11/3616 , G06F11/3624
摘要： A computer program product for code coverage utilizing efficient dynamic mutation of logic (EDML) are provided. A source code is read, and instrumentation points are located. Self Modifying Code (SMC) is inserted at the instrumentation points producing instrumented code. Additional functions are inserted in the source code to enable read and/or reset of code coverage statistics. The instrumented code is compiled, and executables are run for a period of time during which zero or more instrumentation points are executed. In response to executing instrumentation points, instructions are executed to record execution of the instrumented code. Instructions of the instrumented code overwrite themselves at certain points so that a next execution of the instrumentation points skips over the instrumented code at the certain points. Code coverage statistics are gathered and recorded. The code coverage statistics are reset to begin another period of time for gathering code coverage statistics.
摘要翻译： 提供了一种使用有效的逻辑动态变化（EDML）的代码覆盖的计算机程序产品。 读取源代码，并找到检测点。 自动修改代码（SMC）被插入到产生检测代码的仪表点上。 在源代码中插入了附加功能，以实现代码覆盖统计信息的读取和/或复位。 已编制仪器化代码，并且可执行文件运行一段时间，在此期间执行零个或多个检测点。 响应执行的仪表点，执行指令以记录检测代码的执行。 仪器化代码的指令在某些点覆盖自己，以便下一次执行仪表点在特定点上跳过检测代码。 收集和记录代码覆盖率统计信息。 代码覆盖率统计信息被重置为开始另一个时间段来收集代码覆盖统计信息。
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公开(公告)号：US08006126B2
公开(公告)日：2011-08-23
申请号：US12777446
申请日：2010-05-11
IPC分类号： G06F11/00
CPC分类号： G06F11/1076 , G06F2211/1007 , G06F2211/104 , G06F2211/109
摘要： Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums.
摘要翻译： 提供数据验证系统和方法。 数据记录在一个或多个存储介质上的N个数据块中。 独立地与所述N个数据块相关联的第一验证块包括用于验证记录在所述N个数据块中的数据的精度的第一验证信息。 第一验证块与包括第二验证信息的第一验证附录相关联，其中第一验证附录存储在独立于所述一个或多个存储介质的第一存储介质上。
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公开(公告)号：US20100217752A1
公开(公告)日：2010-08-26
申请号：US12777446
申请日：2010-05-11
IPC分类号： G06F17/30
CPC分类号： G06F11/1076 , G06F2211/1007 , G06F2211/104 , G06F2211/109
摘要： Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums.
摘要翻译： 提供数据验证系统和方法。 数据记录在一个或多个存储介质上的N个数据块中。 独立地与所述N个数据块相关联的第一验证块包括用于验证记录在所述N个数据块中的数据的精度的第一验证信息。 第一验证块与包括第二验证信息的第一验证附录相关联，其中第一验证附录存储在独立于所述一个或多个存储介质的第一存储介质上。
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公开(公告)号：US20080282105A1
公开(公告)日：2008-11-13
申请号：US11747188
申请日：2007-05-10
IPC分类号： G06F11/00
CPC分类号： G06F11/1076 , G06F2211/1007 , G06F2211/104 , G06F2211/109
摘要： Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums.
摘要翻译： 提供数据验证系统和方法。 数据记录在一个或多个存储介质上的N个数据块中。 独立地与所述N个数据块相关联的第一验证块包括用于验证记录在所述N个数据块中的数据的精度的第一验证信息。 第一验证块与包括第二验证信息的第一验证附录相关联，其中第一验证附录存储在与所述一个或多个存储介质无关的第一存储介质上。
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公开(公告)号：US07284029B2
公开(公告)日：2007-10-16
申请号：US10702989
申请日：2003-11-06
IPC分类号： G06F7/50
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.
摘要翻译： 一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。 进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。 第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。 由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。 此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。
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公开(公告)号：US06873188B2
公开(公告)日：2005-03-29
申请号：US10242236
申请日：2002-09-12
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.
摘要翻译： 选择器电路和系统在一个时钟周期内进行单和多电平选择，在动态逻辑电路的输出上具有静态开关因子。 实现了具有动态逻辑电路部分和静态逻辑电路部分的单级和多级选择的逻辑器件。 这样，只要逻辑器件执行的布尔运算的值不变，就保持输出逻辑状态。 此外，静态逻辑元件可以执行输出逻辑感应所需的反转，减轻提供双轨动态逻辑实现的需要。 非对称时钟允许预充电晶体管的尺寸伴随减小，因此改善了逻辑元件所需的面积并且消除了对保持器装置的需要。
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20.发明申请Reducing Energy Consumption and Optimizing Workload and Performance in Multi-tier Storage Systems Using Extent-level Dynamic Tiering 有权降低能耗，优化多层次存储系统的工作量和性能，使用层级动态分层公开(公告)号：US20120102350A1
公开(公告)日：2012-04-26
申请号：US12910144
申请日：2010-10-22
CPC分类号： G06F1/3268 , G06F1/3221 , Y02D10/154
摘要： Embodiments of the invention relate to reducing energy consumption and optimizing workload and performance in multi-tier storage systems using extent-level dynamic tiering. An aspect of the invention includes a receiving data access information of a storage extent stored in a storage system and utilization information of storage devices in the storage system. The storage system includes a plurality of storage tiers and each of the plurality of storage tiers is made up of a plurality of storage devices. Storage resources required for each of the plurality of the storage tiers to satisfy the storage extent's performance and capacity requirements are estimated based on the data access information. One storage tier that would incur the lowest power consumption to the storage system for satisfying the storage extent's performance and capacity requirements is determined. The one storage tier is determined by calculating the amount of power that would be consumed by the storage extent in each of the plurality of storage tiers based on the estimated storage resources. At least one storage device in the one storage tier that has available storage resources that would satisfy the storage extent's performance and capacity requirements is determined based on the data access information and utilization information. The storage extent is allocated to the one storage tier and to one storage device (among the at least one storage device) that has the least amount of available storage capacity.
摘要翻译： 本发明的实施例涉及使用范围级动态分层来降低能量消耗并优化多层存储系统中的工作负载和性能。 本发明的一个方面包括存储在存储系统中的存储范围的接收数据访问信息和存储系统中的存储设备的利用信息。 存储系统包括多个存储层，并且多个存储层中的每一个由多个存储装置构成。 基于数据访问信息来估计多个存储层中的每一个所需的存储资源以满足存储范围的性能和容量要求。 确定存储系统的最低功耗的满足存储范围的性能和容量需求的一个存储层。 基于所估计的存储资源，通过计算多个存储层中的每一个中的存储范围将消耗的功率量来确定一个存储层。 基于数据访问信息和利用信息来确定一个存储层中具有满足存储范围的性能和容量需求的可用存储资源的至少一个存储设备。 存储范围被分配给具有最少可用存储容量的一个存储层和一个存储设备（至少一个存储设备中）。
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