公开(公告)号：US20180121564A1

公开(公告)日：2018-05-03

申请号：US15340340

申请日：2016-11-01

Applicant: Wisconsin Alumni Research Foundation

Inventor： Jing Li ,  Jialiang Zhang ,  Soroosh Khoram

IPC: G06F17/30 ,  G11C5/06 ,  G11C7/00

CPC classification number: G06F16/9024 ,  G06F16/90335

Abstract: A computer architecture for graph processing employs a high-bandwidth memory closely coupled to independent processing elements for searching through a graph using a first set of processing elements operating simultaneously to determine neighbors to a current frontier and second processing elements operating simultaneously to determine a next frontier, this process being repeated to search through graph nodes.

公开(公告)号：US20190258401A1

公开(公告)日：2019-08-22

申请号：US15901376

申请日：2018-02-21

Applicant: Wisconsin Alumni Research Foundation

Inventor： Jing Li ,  Jialiang Zhang

IPC: G06F3/06 ,  G06F17/30

Abstract: A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.

公开(公告)号：US20180113839A1

公开(公告)日：2018-04-26

申请号：US15334398

申请日：2016-10-26

Applicant: Wisconsin Alumni Research Foundation

Inventor： Jing Li ,  Soroosh Khoram

IPC: G06F15/78

CPC classification number: G06F15/7839 ,  G06F7/38 ,  G06F15/7821

Abstract: An associative processor separates the arithmetic operation of addition from the carry process to pre-compute contingent carries before the addition which then allows improved parallelism in the addition process. A portion of the contingent carry computation may also be conducted in parallel. The result is higher-speed operations resulting from increased parallelism.

公开(公告)号：US20170163534A1

公开(公告)日：2017-06-08

申请号：US14959614

申请日：2015-12-04

Applicant: Wisconsin Alumni Research Foundation

Inventor： Jing Li

IPC: H04L12/743 ,  G06F13/16 ,  G06F13/28

CPC classification number: H04L45/7457 ,  G06F13/1636 ,  G06F13/287 ,  G11C8/10

Abstract: An associative memory that can be integrated with standard computer memory flexibly reduces its parallelism to match the memory bus speed thereby providing substantial increases in memory density possible by a multiplexing of sense amplifiers that otherwise dominate the memory structure. Apparent parallel operation is provided by an accumulator that reassembles the multiplex data. Higher memory density makes dual use of the associative memory as a content addressable memory and random-access memory possible.