Computer architecture for high-speed, graph-traversal

    公开(公告)号:US10747433B2

    公开(公告)日:2020-08-18

    申请号:US15901376

    申请日:2018-02-21

    Abstract: A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.

    Touch surface for mobile devices using near field light sensing

    公开(公告)号:US10156901B2

    公开(公告)日:2018-12-18

    申请号:US14885490

    申请日:2015-10-16

    Abstract: A virtual touchscreen for mobile devices provides a touchscreen area displaced to a side of the display to eliminate problems of a finger blocking the display during normal touchscreen operation. The virtual touchscreen may be monitored by a sensor system looking edgewise from a housing of the mobile device employing as few as two displaced photodetectors and a correspondingly oriented light source constrained to sensitivity within a narrow fan-shaped light-sensing plane. Extraction of the spatial location of a finger touch within this touchscreen area may be performed by a model of reflected light signals of a finger in different locations calibrated to environmental parameters of finger reflectivity and background reflectivity by a simple calibration process.

    Computer Architecture for High-Speed, Graph-Traversal

    公开(公告)号:US20190258401A1

    公开(公告)日:2019-08-22

    申请号:US15901376

    申请日:2018-02-21

    Abstract: A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.

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