Abstract:
The present disclosure provides a display substrate, display panel, and display device. The display substrate includes: a base substrate having a display area and a periphery area surrounding the display area; a plurality of force sensors disposed in the periphery area; and a substrate layer layered upon the base substrate and disposed under a film layer where the plurality of force sensors are located and including a plurality of strip-shaped convex structures; wherein a portion of each of the plurality of force sensors corresponding to each of the plurality of strip-shaped convex structures is convex, and another portion of each of the plurality of force sensors corresponding to a gap between adjacent two of the plurality of strip-shaped convex structures is concave. The present disclosure achieves that abnormal display will not appear on display panel at display area edge or position corresponding to force sensor, thereby improving display effect.
Abstract:
A display panel and a display device are provided. The display panel has a pixel region and a frame region surrounding the pixel region. The pixel region includes sub-pixels each including a first transistor and a pixel electrode. The plurality of sub-pixels includes display sub-pixels and dummy sub-pixels. At least part of the dummy sub-pixels are antistatic sub-pixels. A data line is configured to provide a driving signal to the display sub-pixels. A scan line is configured to provide scan signal to the display sub-pixels. A first reference signal line is configured to provide static protection reference signal to the antistatic sub-pixels. The first gate electrode of the first transistor of the antistatic sub-pixel is connected to the first drain electrode and a first reference signal line, and the first source electrode of the first transistor of the antistatic sub-pixel is connected to the data line.
Abstract:
Provided are a display panel, a display device, and a display panel control method. The display panel includes a display area and a non-display area. The non-display area includes a first area and a second area, and at least one first force-sensing sensor is provided in the first area and/or the second area. A plurality of touch electrodes and a plurality of touch signal lines respectively electrically connected to each of the touch electrodes are provided in the display area, and the touch signal lines include at least one multiplexed signal line respectively corresponding to each of the at least one first force-sensing sensor. The display area further includes at least one transverse connecting line. The display panel further includes at least one switch device, each of which and a corresponding transverse connecting line are connected in series between a corresponding first force-sensing sensor and a corresponding multiplexed signal line.
Abstract:
An array substrate, a liquid crystal display panel and a liquid crystal display device. The array substrate includes: a plurality of pixel units defined by a plurality of intersecting data lines and scanning lines, wherein each of the plurality of pixel units comprises a thin film transistor and a pixel electrode electrically connected with the thin film transistor; a plurality of common electrode blocks disposed in a layer different from the pixel electrode, the common electrode blocks being reused as touch electrodes; a plurality of sensing lines, each of which is electrically connected with one of the common electrode blocks; and a plurality of auxiliary electrodes disposed in the same layer as the pixel electrode, wherein each of the plurality of auxiliary electrodes is disposed between two adjacent pixel electrodes, and overlapped and electrically connected with one of the sensing lines.
Abstract:
An electro-static discharge protection circuit for a liquid crystal display is disclosed. In response to positive electro-static charges being generated on the signal line, a thin film transistor with a gate electrode connected to the high level signal line is switched on, and the positive electro-static charges are discharged through the switched on thin film transistor. In addition, in response to negative electro-static charges being generated on the signal line, a thin film transistor with a gate electrode connected to the low level signal line is switched on, and the negative electro-static charges are discharged through the switched on thin film transistor.
Abstract:
Disclosed is an array substrate. The array substrate includes a substrate and a pixel unit array. A first side of each row of pixel units is provided with a first scanning line corresponding to the row of pixel units, and the first scanning line is connected to switch elements of first-type pixel units in the row of pixel units; and the second side of each row of pixel units is provided with a second scanning line corresponding to the row of pixel units, and the second scanning line is connected to switch elements of second-type pixel units in the row of pixel units. An active layer structure of the switch element of a second-type pixel unit in an ith row of pixel units has a common region with an active layer structure of the switch element of a first-type pixel unit in an (i+1)th row of pixel units.
Abstract:
An array substrate, including: data lines, scan lines intersecting the data lines; and a plurality of pixel regions; where each of the plurality of pixel regions includes first and second light transmission regions and a light shielding region between the first and second light transmission regions, a first electrode is disposed in the first light transmission region, a second electrode is disposed in the second light transmission region, and a thin film transistor is disposed in the light shielding region, where a drain electrode of the thin film transistor is electrically connected with the first electrode and the second electrode; the data line corresponding to each of the plurality of pixel regions includes a first portion and a second portion extending in two different directions, respectively, the first portion is connected with the second portion via a first connection portion located at the light shielding region.
Abstract:
An array substrate, including: data lines, scan lines intersecting the data lines; and a plurality of pixel regions; where each of the plurality of pixel regions includes first and second light transmission regions and a light shielding region between the first and second light transmission regions, a first electrode is disposed in the first light transmission region, a second electrode is disposed in the second light transmission region, and a thin film transistor is disposed in the light shielding region, where a drain electrode of the thin film transistor is electrically connected with the first electrode and the second electrode; the data line corresponding to each of the plurality of pixel regions includes a first portion and a second portion extending in two different directions, respectively, the first portion is connected with the second portion via a first connection portion located at the light shielding region.
Abstract:
A TFT substrate and a method of manufacturing the TFT array substrate are disclosed. The method includes providing a substrate, forming an organic layer on the substrate, forming a first transparent conductive layer on the organic layer, and forming a photolithography layer on the first transparent conductive layer, where the photolithography layer has an opening. The method also includes patterning the first transparent conductive layer to form a first via hole in the first transparent layer using the photolithography layer as a mask, where the first via hole is aligned with the opening in the photolithography layer, and patterning the organic layer to form a second via hole in the organic using the photolithography layer as a mask, where the second via hole is aligned with the opening in the photolithography layer.
Abstract:
An array substrate and a display panel are provided. The array substrate comprises a display area including a first and a second display area parallelly arranged along a first direction, wherein the second display area includes a first edge portion extending along a second direction; a non-display area including a first and a second non-display area, wherein in the second direction, the first non-display area is disposed at one side of the display area and includes a first sub-non-display area and a second sub-non-display area; at least one notch formed by recessing the first edge portion toward an inside of the second display area; data lines; and at least one driving chip. An orthogonal projection of the at least one driving chip onto the array substrate is at least partially located in the second sub-non-display area. The second non-display area is disposed at perimeter of the at least one notch.