公开(公告)号：US11947409B2

公开(公告)日：2024-04-02

申请号：US17574340

申请日：2022-01-12

Applicant: XILINX, INC.

Inventor： Sarosh I. Azad ,  Aditi R. Ganesan

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/0772 ,  G06F11/1004

Abstract: An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.

公开(公告)号：US11429481B1

公开(公告)日：2022-08-30

申请号：US17178207

申请日：2021-02-17

Applicant: XILINX, INC.

Inventor： Sarosh I. Azad ,  Wern-Yan Koe ,  Amitava Majumdar

IPC: G06F11/10 ,  G06F12/06

Abstract: Embodiments herein describe a hardware based scrubbing scheme where correction logic is integrated with memory elements such that scrubbing is performed by hardware. The correction logic reads the data words stored in the memory element during idle cycles. If a correctable error is detected, the correction logic can then use a subsequent idle cycle to perform a write to correct the error (i.e., replace the corrupted data stored in the memory element with corrected data). By using built-in or integrated correction logic, the embodiments herein do not add extra work for the processor, or can work with applications that do not include a processor. Further, because the correction logic scrubs the memory during idle cycles, correcting bit errors does not have a negative impact on the performance of the memory element. Memory scrubbing can delay the degradation of data error, extending the integrity of the data in the memory.

公开(公告)号：US10042692B1

公开(公告)日：2018-08-07

申请号：US14869821

申请日：2015-09-29

Applicant: Xilinx, Inc.

Inventor： Sarosh I. Azad ,  Bhaarath Kumar ,  Tomai Knopp

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/263

Abstract: The disclosure describes a circuit arrangement that includes a master circuit and a slave circuit. The master circuit generates transactions, and the slave circuit generates responses to the transactions from the master circuit. A first circuit is coupled between the master circuit and the slave circuit. The first circuit determines for each transaction from the master circuit whether the slave circuit generates an expected number of responses within a timeout period. For each transaction for which the slave circuit does not generate the expected number of responses within the timeout period, the first circuit generates and transmits the expected number of responses to the master circuit.

公开(公告)号：US09720868B2

公开(公告)日：2017-08-01

申请号：US14325238

申请日：2014-07-07

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  Sarosh I. Azad

IPC: G06F13/364 ,  G06F13/40 ,  G06F12/14 ,  G06F21/78 ,  G06F21/85

CPC classification number: G06F13/404 ,  G06F12/1441 ,  G06F12/145 ,  G06F21/78 ,  G06F21/85

Abstract: Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address.

公开(公告)号：US20140281716A1

公开(公告)日：2014-09-18

申请号：US13802223

申请日：2013-03-13

Applicant: Xilinx, Inc.

Inventor： Sarosh I. Azad

IPC: G06F11/27

CPC classification number: G06F11/27 ,  G01R31/3167 ,  G01R31/3171 ,  G01R31/31716

Abstract: An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.

Abstract translation: 公开了一种通常涉及片上系统的装置。 在该装置中，片上系统具有至少一个模拟块，输入/输出接口，数据测试块和处理单元。 处理单元耦合到输入/输出接口以控制对至少一个模拟块的访问。 数据测试块通过输入/输出接口耦合到至少一个模拟块。 处理单元耦合到数据测试块并且被配置为执行具有至少一个测试图案的测试代码。 在由处理单元执行的测试代码的控制下的数据测试块被配置为用测试图案测试至少一个模拟块。