公开(公告)号：US20170344482A1

公开(公告)日：2017-11-30

申请号：US15163384

申请日：2016-05-24

Applicant: Xilinx, Inc.

Inventor： Bhaarath Kumar ,  Sarosh I. Azad

IPC: G06F12/0862 ,  G06F13/28 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/0862 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/28 ,  G06F2212/6026 ,  G06F2212/65 ,  G06F2212/68

Abstract: Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (MMU) circuit. Virtual memory access requests sent to a particular port of the MMU circuit are monitored. In response to the satisfaction of a trigger condition, virtual memory pre-fetch requests are generated and transmitted to the MMU circuit using the particular port. Physical access requests from the MMU circuit are monitored for physical addresses corresponding to the virtual memory pre-fetch requests. The physical access requests corresponding to the virtual memory pre-fetch requests are filtered.

公开(公告)号：US09465766B1

公开(公告)日：2016-10-11

申请号：US14065804

申请日：2013-10-29

Applicant: Xilinx, Inc.

Inventor： Tomai Knopp ,  Sarosh I. Azad ,  Bhaarath Kumar

IPC: G06F13/36 ,  G06F13/42

CPC classification number: G06F13/42

Abstract: An apparatus for communication using a master-slave communication protocol includes a master circuit and a slave circuit configured to communicate with each other using a master-slave communication protocol. The apparatus also includes an interface circuit coupled to the master and slave circuits. In response to a first control signal having a first value, the interface circuit forwards messages received from the master circuit to the slave circuit and forwards responses received from the slave circuit to the master circuit. In response to the first control signal having a second value, the interface circuit prevents messages received from the master circuit from being forwarded from the master circuit to the slave circuit.

Abstract translation: 使用主从通信协议的通信装置包括主电路和被配置为使用主 - 从通信协议彼此通信的从电路。 该装置还包括耦合到主电路和从电路的接口电路。 响应于具有第一值的第一控制信号，接口电路将从主电路接收的消息转发到从电路，并将从从电路接收的响应转发给主电路。 响应于具有第二值的第一控制信号，接口电路防止从主电路接收的消息从主电路转发到从电路。

公开(公告)号：US10042692B1

公开(公告)日：2018-08-07

申请号：US14869821

申请日：2015-09-29

Applicant: Xilinx, Inc.

Inventor： Sarosh I. Azad ,  Bhaarath Kumar ,  Tomai Knopp

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/263

Abstract: The disclosure describes a circuit arrangement that includes a master circuit and a slave circuit. The master circuit generates transactions, and the slave circuit generates responses to the transactions from the master circuit. A first circuit is coupled between the master circuit and the slave circuit. The first circuit determines for each transaction from the master circuit whether the slave circuit generates an expected number of responses within a timeout period. For each transaction for which the slave circuit does not generate the expected number of responses within the timeout period, the first circuit generates and transmits the expected number of responses to the master circuit.

公开(公告)号：US10657067B1

公开(公告)日：2020-05-19

申请号：US15262834

申请日：2016-09-12

Applicant: Xilinx, Inc.

Inventor： Sarosh I. Azad ,  Bhaarath Kumar

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/0862

Abstract: A memory management unit circuit includes a plurality of ports with a plurality of translation buffer units. Each translation buffer unit includes a translation lookaside buffer circuit and a translation logic circuit configured to perform virtual to physical address translation using the translation lookaside buffer circuit. A translation lookaside buffer circuit prefetch logic circuit monitors virtual memory access requests received at the corresponding port of the memory management unit circuit and detects satisfaction of at least one trigger condition. In response, address translation prefetch requests are generated. A control circuit transmits the address translation prefetch requests to a physical memory circuit and receives address translation data for populating the translation lookaside buffer.

公开(公告)号：US10402332B2

公开(公告)日：2019-09-03

申请号：US15163384

申请日：2016-05-24

Applicant: Xilinx, Inc.

Inventor： Bhaarath Kumar ,  Sarosh I. Azad

IPC: G06F12/0862 ,  G06F12/1027 ,  G06F12/1009 ,  G06F13/28

Abstract: Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (MMU) circuit. Virtual memory access requests sent to a particular port of the MMU circuit are monitored. In response to the satisfaction of a trigger condition, virtual memory pre-fetch requests are generated and transmitted to the MMU circuit using the particular port. Physical access requests from the MMU circuit are monitored for physical addresses corresponding to the virtual memory pre-fetch requests. The physical access requests corresponding to the virtual memory pre-fetch requests are filtered.