公开(公告)号：US07627070B2

公开(公告)日：2009-12-01

申请号：US11222412

申请日：2005-09-08

Applicant: Xavier Cauchy ,  Eric Salvaire ,  Cédric Force

Inventor： Xavier Cauchy ,  Eric Salvaire ,  Cédric Force

IPC: H03D3/24 ,  H03K19/096

CPC classification number: H04L7/0012 ,  H03K5/26 ,  H04J3/047 ,  H04L7/02 ,  H04N21/242 ,  H04N21/4302

Abstract: A device is for detecting a relative positioning of two clock signals including a fast clock signal and a slow clock signal. The fast clock frequency may be n times greater than a slow clock frequency, and n includes an integer greater than 1. The device includes a phase logic signal generator for generating a phase logic signal from the two clock signals by assigning a predetermined logic value to the phase logic signal when a rising edge of the fast clock signal matches a predetermined location of the slow clock signal.

Abstract translation: 一种装置用于检测包括快速时钟信号和慢时钟信号的两个时钟信号的相对定位。 快速时钟频率可以是慢时钟频率的n倍，并且n包括大于1的整数。该装置包括相位逻辑信号发生器，用于通过将预定逻辑值分配给两个时钟信号来产生相位逻辑信号 当快速时钟信号的上升沿与慢时钟信号的预定位置相匹配时的相位逻辑信号。

公开(公告)号：US20070288691A1

公开(公告)日：2007-12-13

申请号：US11729308

申请日：2007-03-27

Applicant: Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sebastien Ferroussat

Inventor： Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sebastien Ferroussat

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: Data stored in a first memory are processed by a processing device comprising a processor, a second memory, and an interface device interfacing the processing device with the first memory. In the interface device, in order to facilitate transfer of data from the first memory where data are stored in a first data format to the second memory where data are stored in a second data format, a first group of data is received from the first memory, with said group ordered into a sequence corresponding to the first data format. Then at least one second group of data is obtained by ordering said data in the first group into a new sequence which is a function of the first and second data formats. The second group of data is stored in the second memory.

Abstract translation: 存储在第一存储器中的数据由包括处理器，第二存储器和将处理设备与第一存储器连接的接口设备的处理设备处理。 在接口装置中，为了促进将数据以第一数据格式存储的第一存储器的数据传送到以第二数据格式存储数据的第二存储器，从第一存储器接收第一组数据 ，所述组被排序成对应于第一数据格式的序列。 然后通过将第一组中的所述数据排序成作为第一和第二数据格式的函数的新序列来获得至少一个第二组数据。 第二组数据存储在第二个存储器中。

公开(公告)号：US6091270A

公开(公告)日：2000-07-18

申请号：US83549

申请日：1998-05-22

Applicant: Xavier Cauchy

Inventor： Xavier Cauchy

IPC: H03B19/00 ,  H03K5/00

CPC classification number: H03B19/00 ,  H03K5/00006

Abstract: A frequency-doubling block includes an input terminal for the incident signal, a first variable delay cell linked to the input, and an EXCLUSIVE OR gate, one input of which is linked to the output of the first delay cell, the other input of which is linked to the input terminal, and the output of which is able to deliver an output clock signal at twice the frequency of the incident signal. A comparison circuit compares the duty ratio of the output signal with a predetermined reference value and a modulation circuit modulates the value of the first delay as a function of the result of the comparison.

Abstract translation: 倍频块包括用于入射信号的输入端，连接到输入的第一可变延迟单元和一个独占或门，其一个输入端连接到第一延迟单元的输出，其另一个输入端 被连接到输入端子，并且其输出能够以两倍的入射信号的频率传送输出时钟信号。 比较电路将输出信号的占空比与预定参考值进行比较，并且调制电路根据比较结果调制第一延迟的值。

公开(公告)号：US5889787A

公开(公告)日：1999-03-30

申请号：US922611

申请日：1997-09-03

Applicant: Xavier Cauchy

Inventor： Xavier Cauchy

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/822 ,  H01L27/04

CPC classification number: G01R31/31712 ,  G01R31/31701 ,  G01R31/31715 ,  G01R31/318555 ,  G01R31/318572

Abstract: The present invention provides a circuit capable of operating according to a normal operating mode or to a structural operating mode. The test mode is stored in an internal flip-flop via an interface of the circuit. In test mode, the flip-flop is insulated from the interface by multiplexing means. To exit the test mode, an input temporarily dedicated to this function is used, this input being then insulated by multiplexing means from the rest of the circuit.

Abstract translation: 本发明提供一种能够根据正常操作模式或结构操作模式操作的电路。 测试模式通过电路的接口存储在内部触发器中。 在测试模式下，触发器通过复用手段与接口绝缘。 要退出测试模式，使用临时专用于此功能的输入，该输入然后通过多路复用装置与电路的其余部分绝缘。