公开(公告)号：US08264496B2

公开(公告)日：2012-09-11

申请号：US12047336

申请日：2008-03-13

Applicant: Xavier Cauchy ,  Bruno Thery ,  Anthony Philippe ,  Mark Petrus Vos

Inventor： Xavier Cauchy ,  Bruno Thery ,  Anthony Philippe ,  Mark Petrus Vos

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06T1/60 ,  G09G5/395 ,  H04N19/102 ,  H04N19/134 ,  H04N19/176 ,  H04N19/186 ,  H04N19/433

Abstract: An image processing system includes a memory for storing data associated with pixels of images, with the pixels having spatial coordinates in an image coordinate system having first and second axes; a processing device including a processor which processes the associated data; and an interface device which accesses in memory addresses associated with pixels of a block of pixels. In the interface device, access information is received indicating a base memory address, information regarding the dimensions of the block along the axes of the image coordinate system, and a storage method. At least one access rule is selected from multiple rules as a function of the storage method. The memory is accessed at the addresses associated with the pixels in the block, by applying the selected rule starting from the base address and taking into account the dimensions of the block.

Abstract translation: 图像处理系统包括存储器，用于存储与图像像素相关联的数据，其中像素具有在具有第一和第二轴的图像坐标系中的空间坐标; 处理装置，包括处理相关数据的处理器; 以及接口设备，其访问与像素块的像素相关联的存储器地址。 在接口装置中，接收指示基本存储器地址的信息，关于沿着图像坐标系的轴的块的尺寸的信息和存储方法。 作为存储方法的功能，从多个规则中选择至少一个访问规则。 通过从基址开始应用所选择的规则并考虑块的尺寸，在与块中的像素相关联的地址处访问存储器。

公开(公告)号：US08166283B2

公开(公告)日：2012-04-24

申请号：US11502343

申请日：2006-08-10

Applicant: Xavier Cauchy

Inventor： Xavier Cauchy

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F1/00

CPC classification number: H03K4/026 ,  G06F1/02

Abstract: A generator of a signal including a memory in which instructions are stored, each instruction including a code portion and an argument portion; circuitry for successively reading instructions stored in the memory; decoding circuitry capable of receiving, for each read instruction, the code portion of the instruction and of providing an activation signal which depends on the code portion; and circuitry for providing the signal capable of receiving, for each read instruction, the argument portion of the instruction and capable, according to the activation signal, of storing the argument portion and of providing the signal equal to the argument portion or of providing the signal equal to the previously-stored argument portion.

Abstract translation: 包括存储指令的存储器的信号的发生器，每个指令包括代码部分和参数部分; 用于连续读取存储在存储器中的指令的电路; 解码电路能够针对每个读取指令接收指令的代码部分并且提供取决于代码部分的激活信号; 以及用于提供能够为每个读取指令接收指令的参数部分并且能够根据激活信号存储参数部分并且提供等于参量部分的信号或者提供信号的信号的电路 等于先前存储的参数部分。

公开(公告)号：US20100211712A1

公开(公告)日：2010-08-19

申请号：US12707451

申请日：2010-02-17

Applicant: Xavier Cauchy ,  Anthony Philippe ,  Isabelle Faugeras ,  Didier Siron

Inventor： Xavier Cauchy ,  Anthony Philippe ,  Isabelle Faugeras ,  Didier Siron

IPC: G06F13/00

CPC classification number: G06T1/20 ,  G06F9/3877 ,  G06F9/3885 ,  G06F13/4022 ,  G06F2213/0038

Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Abstract translation: 用于处理数字数据的该系统可以包括用于执行基本功能的一组从属处理单元，互连模块，其被设计为与数据传输网络进行通信，并且一方面在处理单元之间传送数据;以及 另一方面，数据传输网络和控制互连模块以控制数据传输的控制器。

公开(公告)号：US20070038878A1

公开(公告)日：2007-02-15

申请号：US11502343

申请日：2006-08-10

Applicant: Xavier Cauchy

Inventor： Xavier Cauchy

IPC: G06F1/00

CPC classification number: H03K4/026 ,  G06F1/02

Abstract: A generator of a signal including a memory in which instructions are stored, each instruction including a code portion and an argument portion; circuitry for successively reading instructions stored in the memory; decoding circuitry capable of receiving, for each read instruction, the code portion of the instruction and of providing an activation signal which depends on the code portion; and circuitry for providing the signal capable of receiving, for each read instruction, the argument portion of the instruction and capable, according to the activation signal, of storing the argument portion and of providing the signal equal to the argument portion or of providing the signal equal to the previously-stored argument portion.

Abstract translation: 包括存储指令的存储器的信号的发生器，每个指令包括代码部分和参数部分; 用于连续读取存储在存储器中的指令的电路; 解码电路能够针对每个读取指令接收指令的代码部分并且提供取决于代码部分的激活信号; 以及用于提供能够为每个读取指令接收指令的参数部分并且能够根据激活信号存储参数部分并且提供等于参数部分的信号或者提供信号的信号的电路 等于先前存储的参数部分。

公开(公告)号：US20060056557A1

公开(公告)日：2006-03-16

申请号：US11222412

申请日：2005-09-08

Applicant: Xavier Cauchy ,  Eric Salvaire ,  Cedric Force

Inventor： Xavier Cauchy ,  Eric Salvaire ,  Cedric Force

IPC: H04L7/00

CPC classification number: H04L7/0012 ,  H03K5/26 ,  H04J3/047 ,  H04L7/02 ,  H04N21/242 ,  H04N21/4302

Abstract: A device is for detecting a relative positioning of two clock signals including a fast clock signal and a slow clock signal. The fast clock frequency may be n times greater than a slow clock frequency, and n includes an integer greater than 1. The device includes a phase logic signal generator for generating a phase logic signal from the two clock signals by assigning a predetermined logic value to the phase logic signal when a rising edge of the fast clock signal matches a predetermined location of the slow clock signal.

公开(公告)号：US08046503B2

公开(公告)日：2011-10-25

申请号：US11752822

申请日：2007-05-23

Applicant: Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sėbastien Ferroussat

Inventor： Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sėbastien Ferroussat

IPC: G06F13/28 ,  G06F17/50

CPC classification number: G06F13/28 ,  G06F2213/0038

Abstract: A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local memory, associated with an indication to the local memory of an address in local memory, and is designed to perform data writes and reads in the local memory via this interface. The DMA controller also comprises a second interface, which in response to a command received from the central processing unit, operations for writing and reading data in the local memory via the first interface. The DMA controller also comprises a third interface with the processing module to transmit to it the data read, via the first interface, in the local memory, this transmission not being associated with an indication to the processing module, by the DMA controller, of an address.

Abstract translation: 片上系统包括CPU，本地存储器，数据处理模块和DMA控制器。 DMA控制器包括用于处理与本地存储器的数据传输相关联的本地存储器中与本地存储器的指示相关联的第一接口，并且被设计为经由该接口执行数据写入和本地存储器中的读取 。 DMA控制器还包括第二接口，其响应于从中央处理单元接收到的命令，经由第一接口在本地存储器中写入和读取数据的操作。 DMA控制器还包括具有处理模块的第三接口，用于向其发送经由第一接口在本地存储器中读取的数据，该传输不与DMA控制器对处理模块的指示相关联， 地址。

公开(公告)号：US20080005390A1

公开(公告)日：2008-01-03

申请号：US11752822

申请日：2007-05-23

Applicant: Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sebastien Ferroussat

Inventor： Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sebastien Ferroussat

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/0038

Abstract: A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local memory, associated with an indication to the local memory of an address in local memory, and is designed to perform data writes and reads in the local memory via this interface. The DMA controller also comprises a second interface, which in response to a command received from the central processing unit, operations for writing and reading data in the local memory via the first interface. The DMA controller also comprises a third interface with the processing module to transmit to it the data read, via the first interface, in the local memory, this transmission not being associated with an indication to the processing module, by the DMA controller, of an address.

Abstract translation: 片上系统包括CPU，本地存储器，数据处理模块和DMA控制器。 DMA控制器包括用于处理与本地存储器的数据传输相关联的本地存储器中与本地存储器的指示相关联的第一接口，并且被设计为经由该接口执行数据写入和本地存储器中的读取 。 DMA控制器还包括第二接口，其响应于从中央处理单元接收到的命令，经由第一接口在本地存储器中写入和读取数据的操作。 DMA控制器还包括具有处理模块的第三接口，用于向其发送经由第一接口在本地存储器中读取的数据，该传输不与DMA控制器对处理模块的指示相关联， 地址。

公开(公告)号：US06097446A

公开(公告)日：2000-08-01

申请号：US863660

申请日：1997-05-27

Applicant: Michel Imbert ,  Serge Volmier ,  Xavier Cauchy

Inventor： Michel Imbert ,  Serge Volmier ,  Xavier Cauchy

IPC: H04N5/06 ,  H04N5/44 ,  H04N7/26 ,  H04N7/56 ,  H04N9/64 ,  H04N5/04 ,  H04N7/01

CPC classification number: H04N7/56 ,  H04N21/440218 ,  H04N5/4401

Abstract: The present invention relates to a method for regulating, in the read mode, memory areas of a circuit for decompressing a video data flow compressed according to an MPEG standard, with respect to the writing rate of the compressed data flow into the memory areas, the decompression circuit issuing a flow of image data at the rate of signals for horizontally and vertically synchronizing the images issued by a circuit for coding according to a color television standard, this method including generating a clock signal having a fixed frequency for reading from the memory areas and for generating the horizontal and vertical synchronization signals, and shifting the occurrence of an edge triggering the vertical synchronization signal based on a signal indicative of the state of a buffer memory associated with the memory areas.

Abstract translation: 本发明涉及一种用于在读取模式下调节用于解压缩根据MPEG标准压缩的视频数据流的电路的存储区域，该方法关于压缩数据流到存储区域的写入速率， 解压缩电路以按照彩色电视标准的用于水平和垂直同步用于编码的电路的图像的信号速率发出图像数据流，该方法包括产生具有固定频率的时钟信号以从存储区域读取 并且用于产生水平和垂直同步信号，并且基于指示与存储器区域相关联的缓冲存储器的状态的信号来移动触发垂直同步信号的边沿的出现。

公开(公告)号：US08527683B2

公开(公告)日：2013-09-03

申请号：US12707451

申请日：2010-02-17

Applicant: Xavier Cauchy ,  Anthony Philippe ,  Isabelle Faugeras ,  Didier Siron

Inventor： Xavier Cauchy ,  Anthony Philippe ,  Isabelle Faugeras ,  Didier Siron

IPC: G06F13/00

CPC classification number: G06T1/20 ,  G06F9/3877 ,  G06F9/3885 ,  G06F13/4022 ,  G06F2213/0038

Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Abstract translation: 用于处理数字数据的该系统可以包括用于执行基本功能的一组从属处理单元，互连模块，其被设计为与数据传输网络进行通信，并且一方面在处理单元之间传送数据;以及 另一方面，数据传输网络和控制互连模块以控制数据传输的控制器。

公开(公告)号：US07769965B2

公开(公告)日：2010-08-03

申请号：US11729308

申请日：2007-03-27

Applicant: Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sébastien Ferroussat

Inventor： Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sébastien Ferroussat

IPC: G06F12/00 ,  G06F17/30

CPC classification number: G06F13/28

Abstract: Data stored in a first memory are processed by a processing device comprising a processor, a second memory, and an interface device interfacing the processing of data from the first memory. In the interface device, in order to facilitate transfer of data from the first memory where data are stored in a first data format to the second memory where data are stored in a second data format, a first group of data is received from the first memory, with said group ordered into a sequence corresponding to the first data format. Then at least one second group of data is obtained by ordering said data in the first group into a new sequence which is a function of the first and second data formats. The second group of data is stored in the second memory.

Abstract translation: 存储在第一存储器中的数据由包括处理器，第二存储器和与来自第一存储器的数据的处理接口的接口设备的处理设备处理。 在接口装置中，为了促进将数据以第一数据格式存储的第一存储器的数据传送到以第二数据格式存储数据的第二存储器，从第一存储器接收第一组数据 ，所述组被排序成对应于第一数据格式的序列。 然后通过将第一组中的所述数据排序成作为第一和第二数据格式的函数的新序列来获得至少一个第二组数据。 第二组数据存储在第二个存储器中。