公开(公告)号：US10893005B2

公开(公告)日：2021-01-12

申请号：US16133357

申请日：2018-09-17

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Jun Liu ,  Raymond Kong ,  Herve Alexanian

IPC: H04L12/931 ,  G06F15/78 ,  H04L12/933 ,  H04L12/761

Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

公开(公告)号：US10796058B1

公开(公告)日：2020-10-06

申请号：US16141723

申请日：2018-09-25

Applicant: Xilinx, Inc.

Inventor： Nicholas A. Mezei ,  Steven Banks ,  Meiwei Wu ,  Raymond Kong

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/3312

Abstract: A platform design including a module black-box instance is loaded into computer hardware. Using the computer hardware, synchronous boundary crossings between a static region and the module black-box instance of the platform design are identified and objects of the platform design included in the synchronous boundary crossings are marked. Using the computer hardware, unmarked objects are removed from the platform design to generate a shell circuit design. A custom circuit design is implemented based on the shell circuit design and timing constraints corresponding to objects remaining in the shell circuit design.

公开(公告)号：US10608641B2

公开(公告)日：2020-03-31

申请号：US16041602

申请日：2018-07-20

Applicant: Xilinx, Inc.

Inventor： Hao Yu ,  Raymond Kong ,  Brian S. Martin ,  Jun Liu

IPC: G06F17/50 ,  G06F15/78 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17736 ,  H03K19/17728 ,  H03K19/177

Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.